Amplifier arrangement and switched capacitor integrator

A switched capacitor integrator comprising:

• an amplifier arrangement, comprising:
• a first differential stage comprising a first and a second transistor;
• a second differential stage comprising a first, a second, a third and a fourth transistor, the first and the second transistors of the second differential stage having a common source connection coupled to a drain terminal of the first transistor of the first differential stage, and the third and the fourth transistors of the second differential stage having a common source connection coupled to a drain terminal of the second transistor of the first differential stage;
• a first complementary differential stage comprising a first and a second complementary transistor having opposite conductivity type compared to the transistors of the first differential stage;
• a second complementary differential stage comprising a first, a second, a third and a fourth complementary transistor having opposite conductivity type compared to the transistors of the second differential stage, the first and the second complementary transistors of the second complementary differential stage having a common source connection coupled to a drain terminal of the first complementary transistor of the first complementary differential stage, and the third and the fourth complementary transistors of the second complementary differential stage having a common source connection coupled to a drain terminal of the second complementary transistor of the first complementary differential stage;
• a first, a second, a third and a fourth pair of distinct input terminals;
• and
• a pair of output terminals;
• a first, a second, a third and a fourth pair of sampling capacitors that are coupled to a pair of common input terminals by at least one pair of first switching elements and are coupled to the first, the second, the third and the fourth pair of input terminals, respectively, by respective pairs of second switching elements;
• a first, a second, a third and a fourth pair of feedback capacitors that are coupled between the pair of output terminals and the first, the second, the third and the fourth pair of input terminals, respectively;
• a first, a second, a third and a fourth common mode input for applying respective common mode voltages, the common mode inputs being coupled to the first, the second, the third and the fourth pair of sampling capacitors, respectively, by further respective pairs of first switching elements;
• and
• at least one further second switching element for connecting the sampling capacitors together,
• wherein
• the complementary transistors of the second complementary differential stage are symmetrically connected to the transistors of the second differential stage such that respective first, second, third and fourth current paths are formed,
• the pair of output terminals is coupled to the first and the fourth current path,
• gate terminals of the transistors of the first differential stage are coupled to the first pair of input terminals,
• gate terminals of the transistors of the second differential stage are coupled to the second pair of input terminals,
• gate terminals of the complementary transistors of the first complementary differential stage are coupled to the third pair of input terminals, and
• gate terminals of the complementary transistors of the second complementary differential stage are coupled to the fourth pair of input terminals.