Clock distribution

Clock distribution circuitry comprising:

• a plurality of first buffers and second buffers, the first and second buffers being inverting buffers;
• and
• control circuitry configured to generate first, second, third and fourth control signals,
• wherein:
• the first buffers each comprise a pull-up circuit comprising one or more pull-up transistors connected for bulk-voltage control by the first control signal and a pull-down circuit comprising one or more pull-down transistors connected for bulk-voltage control by the second control signal;
• the second buffers each comprise a pull-up circuit comprising one or more pull-up transistors connected for bulk-voltage control by the third control signal and a pull-down circuit comprising one or more pull-down transistors connected for bulk-voltage control by the fourth control signal;
• one of the first buffers and one of the second buffers are connected in series as a first buffer pair to form a first clock path for propagation of a clock signal therealong in a propagation direction;
• another one of the first buffers and another one of the second buffers are connected in series as a second buffer pair to form a second clock path for propagation of a clock signal therealong in the propagation direction;
• and
• the control circuitry is configured to control at least one of the first to fourth control signals as a variable signal,
• wherein the buffers are larger in transistor size from buffer to buffer along each clock path in the propagation direction.

Clock distribution circuitry comprising:

• a plurality of first buffers and second buffers, the first and second buffers being inverting buffers;
• and
• control circuitry configured to generate first, second, third and fourth control signals,
• wherein:
• the first buffers each comprise a pull-up circuit comprising one or more pull-up transistors connected for bulk-voltage control by the first control signal and a pull-down circuit comprising one or more pull-down transistors connected for bulk-voltage control by the second control signal;
• the second buffers each comprise a pull-up circuit comprising one or more pull-up transistors connected for bulk-voltage control by the third control signal and a pull-down circuit comprising one or more pull-down transistors connected for bulk-voltage control by the fourth control signal;
• one of the first buffers and one of the second buffers are connected in series as a first buffer pair to form a first clock path for propagation of a clock signal therealong in a propagation direction;
• another one of the first buffers and another one of the second buffers are connected in series as a second buffer pair to form a second clock path for propagation of a clock signal therealong in the propagation direction;
• the control circuitry is configured to control at least one of the first to fourth control signals as a variable signal;
• in the first buffer pair, the second buffer is connected in series after the first buffer in the propagation direction;
• in the second buffer pair, the first buffer is connected in series after the second buffer in the propagation direction;
• the first and second clock paths are arranged in parallel to one another, and connected to propagate complementary clock signals in parallel in the propagation direction;
• cross-coupled inverters are connected between corresponding or like positions along the parallel clock paths;
• each cross-coupled inverter pair comprises another one of the first buffers and another one of the second buffers;
• and
• for each cross-coupled inverter pair, the first buffer of the cross-coupled inverter pair is connected to receive a clock signal output from a second buffer of one of the parallel clock paths, and the second buffer of the cross-coupled inverter pair is connected to receive a clock signal output from a first buffer of the other of the parallel clock paths.