Memory arrays

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region;
• a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure;
• and
• a sense line electrically coupled to multiple of the second source/drain regions of individual of the transistors.

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region;
• a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the elevationally-extending sense-line structure;
• and
• a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure.

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
• a sense line electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers;
• and
• individual of the tiers of memory cells comprising two of the memory cells one of which is directly above the other in that individual tier of memory cells.

A memory array, comprising:

• vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
• a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions;
• and
• a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
• a sense line electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers;
• and
• individual of the tiers of memory cells comprising the gate and another gate, one of the gate and the another gate being directly above the other in that individual tier of memory cells.