Provision of structural integrity in memory device
AssigneeIntel Corporation
InventorMichael J. Bernhardt
Life of this patent
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Abstract
Embodiments of the present disclosure are directed towards techniques to provide structural integrity for a memory device comprising a memory array. In one embodiment, the device may comprise a memory array having at least a plurality of wordlines disposed in a memory region of a die, and a first fill layer deposited between adjacent wordlines of the plurality of wordlines in the memory region, to provide structural integrity for the memory array. At least a portion of a periphery region of the die adjacent to the memory region may be substantially filled with a second fill layer that is different than the first fill layer. Other embodiments may be described and/or claimed.
Claims9
An apparatus, comprising:
- a memory region that includes a plurality of wordlines disposed adjacent each other, the wordlines having first sides and second sides opposite the first sides, wherein the first sides of the wordlines define a plane in a die, wherein the plurality of wordlines form a memory array;
- a periphery region disposed adjacent to the memory region, wherein the periphery region includes a first side and a second side opposite the first side, wherein the first side of the periphery region further defines the plane of the die;
- a first fill layer deposited substantially between adjacent wordlines of the plurality of wordlines, to provide structural integrity for the memory array;
- and
- a second fill layer deposited in the periphery region to substantially fill at least a portion of the periphery region, wherein the second fill layer covers the first side of the at least a portion of the periphery region, wherein the second fill layer comprises inorganic dielectric material.
Dependencies are inferred from the claim text.