MOSFET based isolation circuit

A system comprising:

• a system ground;
• a first isolation circuit comprising:
• a first bipolar junction transistor (BJT), wherein a base of the first BJT is coupled to the system ground;
• a first metal oxide semiconductor field effect transistor (MOSFET);
• a second MOSFET, wherein a gate of the first MOSFET is electrically connected to both a gate of the second MOSFET and to a collector terminal of the first BJT;
• a first voltage node electrically connected to a drain terminal of the first MOSFET;
• and
• a second isolation circuit comprising:
• a second BJT, wherein a base of the second BJT is coupled to the system ground;
• a third MOSFET;
• a fourth MOSFET, wherein a gate of the third MOSFET is electrically connected to both a gate of the fourth MOSFET and to a collector terminal of the second BJT;
• a second voltage node is electrically connected to a drain terminal of the third MOSFET;
• and
• processing circuitry configured to:
• control the first BJT via a first control signal line electrically connected to an emitter terminal of the first BJT;
• and
• control the second BJT via a second control signal line electrically connected to an emitter terminal of the second BJT.

A method comprising:

• sending, by processing circuitry, a first control signal comprising a LOW logic level to a first isolation circuit, wherein the first isolation circuit comprises a first bipolar junction transistor (BJT) and wherein the processing circuitry sends the first control signal to an emitter of the first BJT;
• in response to the processing circuitry sending the LOW logic level, isolating, by the first isolation circuit, a first voltage node from a system ground;
• sending, by the processing circuitry, a second control signal comprising a HIGH logic level to a second isolation circuit, wherein the second isolation circuit comprises a second BJT and wherein the processing circuitry sends the second control signal to an emitter of the second BJT;
• in response to the processing circuitry sending the HIGH logic level, connecting, by the second isolation circuit, a second voltage node to the system ground,
• sending, by the processing circuitry, the HIGH logic level to the first isolation circuit at a first time;
• sending, by the processing circuitry, the HIGH logic level to the second isolation circuit at a second time different than the first time.