Bitcell state retention

A system comprising:

• a display;
• a memory;
• a processor to write data in and read data from the memory;
• and
• a video controller to display information to the display based on data in the memory;
• wherein the memory includes:
• a magnetoresistive random access memory (MRAM) array having first and second rows of bitcells, respective bitcells separately including a ferromagnetic device having a polarization that indicates a first or second bit value storage state;
• a first word line coupled with bitcells of the first row;
• a second word line coupled with bitcells of the second row;
• and
• control circuitry including logic, the logic to:
• cause an access to a bitcell of the first row, the access to generate a first magnetic field;
• cause a second magnetic field to be generated in the bitcell of the second row to compensate for the first magnetic field to mitigate an impact of the first magnetic field on the bit value storage state of the bitcell of the second row
• generate a first word line control signal of a first polarity on the first word line, the first word line control signal to cause the first magnetic field;
• generate a word line compensation control signal of a second polarity on the second word line to cause the second magnetic field to be generated in the bitcell of the second row to compensate for the first magnetic field;
• determine whether the access to the bitcell of the first row causes a count of consecutive accesses to the bitcell of the first row to exceed a threshold value;
• and
• suspend one or more subsequent accesses to the bitcell of the first row for a suspension interval if the count exceeds the threshold value, to mitigate an impact of the first magnetic field on a bit value storage state of the bitcell of the second row.

A method comprising:

• accessing a bitcell of a first row of bitcells of a magnetoresistive random access memory (MRAM) array having first and second rows of bitcells, respective bitcells separately including a ferromagnetic device having a polarization that indicates a first or second bit value storage state, the access to generate a first magnetic field, a first word line is coupled with bitcells of the first row and a second word line is coupled with bitcells of the second row;
• causing a second magnetic field to be generated in the bitcell of the second row to compensate for the first magnetic field to mitigate an impact of the first magnetic field on the bit value storage state of the bitcell of the second row;
• generating a first word line control signal of a first polarity on the first word line, the first word line control signal to cause the first magnetic field;
• generating a word line compensation control signal of a second polarity on the second word line to cause the second magnetic field to be generated in the bitcell of the second row to compensate for the first magnetic field;
• determining whether the access to the bitcell of the first row causes a count of consecutive accesses to the bitcell of the first row to exceed a threshold value;
• and
• suspending one or more subsequent accesses to the bitcell of the first row for a suspension interval if the count exceeds the threshold value, to mitigate an impact of the first magnetic field on a bit value storage state of the bitcell of the second row.