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US 10,594,474 B2Granted
Architecture and instruction set for implementing advanced encryption standard (AES)
AssigneeIntel Corporation
InventorsShay Gueron, Wajdi K. Feghali, Vinodh Gopal
Life of this patent
Estimating the term…
Abstract
A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
Claims21
A processor comprising:
- a plurality of cores;
- a level 1 (L1) instruction cache to store instructions, including a Single Instruction Multiple Data (SIMD) instruction;
- a level 1 (L1) data cache to store data;
- instruction fetch circuitry to fetch the instructions from the L1 instruction cache;
- decode circuitry to decode the SIMD instruction, wherein the SIMD instruction specifies that only a last encryption round of an Advanced Encryption Standard (AES) encryption operation is to be performed, and wherein the SIMD instruction has a parameter that is dedicated to specification of whether encryption or decryption is to be performed;
- a Read Only Memory (ROM) to store micro operations for the SIMD instruction;
- a first 128-bit source register, of a set of registers, to store input data to be encrypted by the last encryption round of the AES encryption operation;
- a second 128-bit source register, of the set of registers, to store a round key to be used for the last encryption round of the AES encryption operation;
- and
- an execution circuit including AES execution circuitry to execute the micro operations for the SIMD instruction to perform the last encryption round of the AES encryption operation, the last encryption round to encrypt the input data from the first 128-bit source register using the round key from the second 128-bit source register, and to store a result of the last encryption round of the AES encryption operation in a 128-bit destination within the set of registers.
7 more elements
A processor comprising:
- a plurality of cores, including a first core comprising:
- a level 1 (L1) instruction cache;
- a level 1 (L1) data cache to store data;
- instruction fetch circuitry to fetch instructions;
- a decoder to decode the instructions, including a Single Instruction Multiple Data (SIMD) instruction, wherein the SIMD instruction specifies that only a last encryption round of an Advanced Encryption Standard (AES) encryption operation, and wherein the SIMD instruction has one or more bits that are dedicated to specification of whether or not an AES round to be performed is an AES last round;
- a Read Only Memory (ROM) to store micro operations for the SIMD instruction;
- a first 128-bit source register to store input data to be encrypted by the last encryption round of the AES encryption operation;
- a second 128-bit source register to store a round key to be used for the last encryption round of the AES encryption operation;
- and
- an execution unit to execute the micro operations for the SIMD instruction to perform the last encryption round of the AES encryption operation, the last encryption round to encrypt the input data from the first 128-bit source register using the round key from the second 128-bit source register, and to store a result of the last encryption round of the AES encryption operation in a 128-bit destination storage location.
7 more elements
A processor comprising:
- a plurality of cores, including a first core comprising:
- a level 1 (L1) instruction cache;
- a level 1 (L1) data cache to store data;
- instruction fetch circuitry to fetch instructions;
- a decoder to decode the instructions, including a Single Instruction Multiple Data (SIMD) instruction, wherein the-SIMD instruction specifies that only a last encryption round of an Advanced Encryption Standard (AES) encryption operation is to be performed, wherein the SIMD instruction has a parameter that is dedicated to specification of whether or not a round to be performed is a last round, and wherein the SIMD instruction has a parameter to specify whether the round to be performed is an encryption round or an decryption round;
- a Read Only Memory (ROM) to store micro operations for the SIMD instruction;
- a first 128-bit source register, of a register file, to store input data to be encrypted by the last encryption round of the AES encryption operation, wherein the first 128-bit source register is an XMM register;
- a second 128-bit source register, of the register file, to store a round key to be used for the last encryption round of the AES encryption operation;
- and
- an execution unit to execute the micro operations for the SIMD instruction to perform the last encryption round of the AES encryption operation, the last encryption round to encrypt the input data from the first 128-bit source register using the round key from the second 128-bit source register, and to store a result of the last encryption round of the AES encryption operation in a 128-bit destination in the register file.
7 more elements
Dependencies are inferred from the claim text.