Method for generating parity check matrix for low density parity check coding

A network component, comprising:

• a read only memory comprising at least one parity portion of a mother parity check matrix (PCM) and a lifting table, the lifting table comprises a plurality of circulant sizes with each circulant size corresponding to a lifting function for generating PCMs from the mother PCM for quasi-cyclic low density parity check (QC-LDPC) coding;
• and
• a parity bit generator configured to:
• receive a source word to be encoded using a QC-LDPC code;
• select, based on a bit length of the source word and a code rate used to encode the source word, a first circulant size Z and a first lifting function corresponding to the first circulant size Z from the lifting table for generating a first PCM of the QC-LDPC code, the first circulant size Z being used to partition the first PCM into a plurality of Z*Z matrices, and each of the plurality of Z*Z matrices being represented by a shift value, wherein the first lifting function indicates a manner of generating shift values of the plurality of Z*Z matrices from the mother PCM;
• generate the shift values of the plurality of Z*Z matrices based on the at least one parity portion of the mother PCM according to the first circulant size Z and using the first lifting function to form the first PCM;
• generate parity bits for the source word using the first PCM of the QC-LDPC code according to a LDPC coding technique;
• and
• perform parity check of the source word using the parity bits to verify the source word.

A network component, comprising:

• a read only memory comprising at least one parity portion of a mother parity check matrix (PCM) and a lifting table, the lifting table comprises a plurality of circulant sizes with each circulant size corresponding to a lifting function for generating PCMs from the mother PCM for quasi-cyclic low density parity check (QC-LDPC) coding;
• an input/output memory;
• and
• a check node processor configured to:
• receive a N-bit code word that is generated from a K-bit source word encoded using a QC-LDPC code, wherein the N-bit code word comprises information of the K-bit source word and a parity check portion;
• select, based on a bit length of the K-bit source word and a code rate used to encode the K-bit source word, a first circulant size Z and a first lifting function corresponding to the first circulant size Z from the lifting table for generating a first PCM of the QC-LDPC code, the first circulant size Z being used to partition the first PCM into a plurality of Z*Z matrices, and each of the plurality of Z*Z matrices being represented by a shift value, wherein the first lifting function indicates a manner of generating shift values of the plurality of Z*Z matrices from the mother PCM;
• generate the shift values of the plurality of Z*Z matrices based on the at least one parity portion of the mother PCM according to the first circulant size Z and using the first lifting function to form the first PCM;
• decode the N-bit code word using the first PCM according to a LDPC coding technique to generate the K-bit source word;
• and
• store the K-bit source word in the input/output memory.

A method for decoding data, comprising:

• receiving an N-bit code word that is generated from a K-bit source word encoded using a quasi-cyclic low density parity check (QC-LDPC) code, wherein the N-bit code word comprises information of the K-bit source word and a parity check portion;
• selecting, based on a bit length of the K-bit source word and a code rate used to encode the K-bit source word, a first circulant size Z from a plurality of circulant sizes and a first lifting function from a plurality of lifting functions for generating a PCM of the QC-LDPC code, the first circulant size Z being used to partition the PCM into a plurality of Z*Z matrices, and each of the plurality of Z*Z matrices being represented by a shift value, wherein the first lifting function indicates a manner of generating shift values of the plurality of Z*Z matrices from a plurality of predetermined shift values;
• generate the shift values of the plurality of Z*Z matrices from the plurality of predetermined shift values according to the first circulant size Z using the first lifting function to construct the PCM;
• decoding the N-bit code word using the PCM to generate the K-bit source word;
• and
• storing the K-bit source word in input/output memory.