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US 10,594,337 B2Granted
Maximum transition avoidance (MTA) encoding
AssigneeNVIDIA Corporation
InventorsSunil Sudhakaran, Russ Newcomb, Rohit Rathi
Life of this patent
Estimating the term…
Abstract
A circuit includes a splitter to extract L bits from each of a plurality of N-bit transmissions on a data bus, a decoder to generate output data comprising N-L bits of each N-bit transmission, and a delay circuit to apply the L bits for a previous transmission to control the inversion of a current transmission at the decoder.
Claims21
A circuit comprising:
- a splitter to extract one bit each from consecutive code words received on a data bus;
- a decoder to generate data words from the code words;
- a delay circuit to cause the extracted bits to be received by the decoder after a delay from the decoder receiving the code words;
- and
- an interleaver to combine the data words from the decoder with bits received on a data bus inversion (DBI) line of the data bus.
2 more elements
A circuit comprising:
- a splitter to extract L bits from each of a plurality of N-bit transmissions on a data bus wherein L is less than N;
- a decoder to generate output data comprising N-L bits of each N-bit transmission;
- and
- a delay circuit to apply the L bits extracted from a first N-bit transmission to control inversion of a second N-bit transmission at the decoder, the first N-bit transmission preceding the second N-bit transmission.
1 more element
A digital receiver comprising:
- an input for a multi-line data bus;
- a decoder comprising:
- a first input coupled to the multi-line data bus;
- a second input coupled to the multi-line data bus via a delay circuit;
- a splitter to extract one bit each from consecutive code words received on the multi-line data bus;
- a decoder block to generate data words from the code words;
- the delay circuit to cause the extracted bits to be received by the decoder block after a delay from the decoder block receiving the code words;
- and
- an interleaver to combine the data words from the decoder block with bits received on a data bus inversion (DBI) line of the multi-line data bus.
6 more elements
Dependencies are inferred from the claim text.