Apparatus comprising a phase-locked loop

A radar receiver comprising:

• a first phase-locked loop comprising:
• a phase detector, arranged to receive a reference clock signal and a feedback clock signal and to output a frequency control signal based on a phase difference between the reference clock signal and the feedback clock signal;
• a variable-frequency oscillator arranged to output an oscillator signal having a frequency dependent on said frequency control signal;
• first divider circuitry for generating said feedback clock signal by frequency-dividing said oscillator signal;
• and
• second divider circuitry for generating an output clock signal by frequency-dividing said oscillator signal, a phase relation between said first divider circuitry and said second divider circuitry adjustable to delay or advance said output clock signal relative to said feedback clock signal by a multiple of one half of a period of said oscillator signal.

An apparatus comprising:

• a first phase-locked loop comprising:
• a phase detector, arranged to receive a reference clock signal and a feedback clock signal and to output a frequency control signal based on a phase difference between the reference clock signal and the feedback clock signal;
• a variable-frequency oscillator arranged to output an oscillator signal having a frequency dependent on said frequency control signal;
• first divider circuitry for generating said feedback clock signal by frequency-dividing said oscillator signal;
• second divider circuitry for generating an output clock signal by frequency-dividing said oscillator signal, a phase relation between said first divider circuitry and said second divider circuitry adjustable to delay or advance said output clock signal relative to said feedback clock signal;
• and
• circuitry for re-clocking said feedback clock signal based on said output clock signal.

A radar transceiver comprising a first integrated chip, the first integrated chip comprising:

• a first phase-locked loop comprising:
• a phase detector, arranged to receive a reference clock signal and a feedback clock signal and to output a frequency control signal based on a phase difference between the reference clock signal and the feedback clock signal;
• a variable-frequency oscillator arranged to output an oscillator signal having a frequency dependent on said frequency control signal;
• first divider circuitry for generating said feedback clock signal by frequency-dividing said oscillator signal;
• and
• second divider circuitry for generating an output clock signal by frequency-dividing said oscillator signal;
• wherein a phase relation between said first divider circuitry and said second divider circuitry is adjustable to delay or advance said output clock signal relative to said feedback clock signal;
• and
• a first ADC arranged to receive said output clock signal.