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US 10,594,325 B2Granted
Fast wakeup for crystal oscillator
AssigneeShenzhen Goodix Technology Co., Ltd.
InventorsMohamed Aboudina, Ahmed Emira, Faisal Hussien
Life of this patent
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Abstract
Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.
Claims20
A method for fast wakeup of a clock system having a crystal oscillator coupled with a phase-locked loop (PLL), the method comprising:
- setting the PLL to a chirp mode, thereby configuring a control voltage input of a voltage-controlled oscillator (VCO) of the PLL to be regulated by a sweep voltage;
- with the PLL in the chirp mode:
- obtaining a retained coarse code for the VCO, the retained coarse code previously determined as an ultimate coarse code used in a prior wakeup routine of the crystal oscillator, the ultimate coarse code corresponding to a coarse-tuned output frequency of the VCO that approximates a predetermined multiple of a reference frequency output by the crystal oscillator at steady state operation of the crystal oscillator;
- applying the retained coarse code to tune, according to the coarse-tuned output frequency, a PLL output frequency of a PLL output signal generated by the VCO;
- outputting by the PLL to the crystal oscillator a chirp signal at a chirp frequency that is divided down from the VCO frequency by the predetermined multiple to approximate the reference frequency;
- and
- sweeping the sweep voltage over a predefined voltage range, thereby sweeping the chirp frequency over a frequency range that comprises a target stimulating frequency of the crystal oscillator, such that outputting the chirp signal at the target stimulating frequency stimulates the crystal oscillator to oscillate at the reference frequency;
- and
- setting the PLL to an operating mode responsive to detecting the steady state operation of the crystal oscillator, such that, in the normal operating mode, the control voltage of the VCO is regulated by a feedback loop of the PLL as a function of a reference clock signal received at the reference frequency from the crystal oscillator.
6 more elements
A clock signal generation system with fast oscillator wakeup, the system comprising:
- a phase-locked loop (PLL) comprising:
- a reference input to couple with a reference output of a crystal oscillator to receive a reference clock signal from the crystal oscillator at a reference frequency;
- a feedback loop to generate a PLL output signal as a predetermined multiple of the reference clock signal, the feedback loop comprising a loop regulation block and a voltage controlled oscillator (VCO) block, the PLL output signal generated by the VCO block at a PLL output frequency as a function of a control voltage input;
- a chirp output to communicate a chirp signal to a chirp input of the crystal oscillator, such that the chirp signal has a chirp frequency that is divided down from PLL output frequency of the PLL output signal by the predetermined multiple to approximate the reference clock signal;
- and
- a mode selector to select between a chirp mode and an operating mode, such that:
- with the mode selector in the chirp mode, the control voltage input is coupled with a sweep voltage, such that the PLL output frequency is a function of a retained coarse code and the sweep voltage, and sweeping the sweep voltage over a predefined voltage range causes the chirp frequency to sweep over a frequency range that comprises a target stimulating frequency of the crystal oscillator, the retained coarse code previously determined as an ultimate coarse code used in a prior wakeup routine of the PLL, such that the ultimate coarse code corresponding to a coarse-tuned output frequency of the VCO block that approximates the predetermined multiple of the reference clock signal at steady state operation of the crystal oscillator;
- and
- with the mode selector in the operating mode, the control voltage input is coupled with the loop regulation block, such that the PLL output frequency is a function of the reference frequency.
6 more elements
A system for fast wakeup of a clock system having a crystal oscillator coupled with a phase-locked loop (PLL), the system comprising:
- a processor;
- processor-readable memory having, stored thereon, instructions, which, when executed, cause the processor to perform steps comprising:
- receiving a wakeup instruction to wake the clock system from a sleep mode;
- setting, responsive to the wakeup instruction, the PLL to a chirp mode, thereby:
- applying a retained coarse code to a voltage-controlled oscillator (VCO) to tune a PLL output frequency of a PLL output signal generated by the VCO to a coarse-tuned output frequency that is previously determined as approximating a predetermined multiple of a reference frequency output by the crystal oscillator at steady state operation of the crystal oscillator;
- configuring a control voltage input of the VCO of the PLL to be regulated by a sweep voltage;
- and
- sweeping the sweep voltage over a predefined voltage range, thereby sweeping a chirp frequency of a chirp signal over a frequency range that comprises a target stimulating frequency of the crystal oscillator, the chirp frequency divided down from the VCO frequency by the predetermined multiple to approximate the reference frequency, such that outputting the chirp signal by the PLL to the crystal oscillator at the target stimulating frequency stimulates the crystal oscillator to oscillate at the reference frequency;
- and
- setting the PLL to an operating mode responsive to detecting the steady state operation of the crystal oscillator, thereby configuring the control voltage of the VCO to be regulated by a feedback loop of the PLL as a function of a reference clock signal received at the reference frequency from the crystal oscillator.
7 more elements
Dependencies are inferred from the claim text.