Mitigation of simultaneous switching output effects

A method of reducing simultaneous switching output (SSO) noise in a multi-channel device, comprising:

• setting a counter i at 1;
• calculating a worst case scenario current for a channel of the device using signal integrity-power integrity (SI-PI) simulation;
• setting a delay for spreading switching of channels of the device evenly over a bit period using a spacing of i multiplied by the bit period divided by a number of channels in the device;
• determining whether a worst case skew for a channel of the device exceeds the delay;
• when the worst case skew does not exceed the delay, performing a layout implementation to spread the channel switching evenly over the bit period using the delay between each channel switching;
• and
• when the worst case skew exceeds the delay:
• performing an SI-PI simulation to determine a maximum current for evenly spreading switching of the channels over the bit period;
• increasing the counter by one, and setting a new delay of i multiplied by the hit period divided by the number of channels in the device;
• grouping the channels into groups of i channels per group,
• performing an SI-PI simulation to determine a new maximum current when switching the groups of channels over the bit period using the new delay between each group of channels switching;
• comparing the new maximum current with the maximum current;
• when the new maximum current is less than the maximum current, repeating increasing the counter, grouping the channels, performing a simulation, and comparing the new maximum current with the previous new maximum current until the new maximum current is equal to or greater than the previous new maximum current.

A method of reducing simultaneous switching output noise in a multi-channel device, comprising:

• determining, using signal integrity-power integrity (SI-PI) simulation, a first switching current for a plurality of independent input/output (I/O) channels of the device switching simultaneously;
• determining an initial delay for switching the channels evenly distributed over a bit period;
• determining, using SI-PI simulation, whether a second switching current for the plurality of I/O channels switching evenly over a known bit period using a delay of the bit period divided by the number of channels in the plurality of channels is less than the first switching current;
• when the second switching current is less than the first switching current, determining, using SI-PI simulation, a new second switching current by grouping the plurality of channels into groups using a longer delay;
• repeating determining a second switching current, comparing, and determining whether grouping the plurality of channels until the determined new switching current is greater than a previous new switching current.