Multi-path amplifier circuit or system and methods of implementation thereof

A Doherty power amplifier comprising:

• a first semiconductor die with an integrated first transistor having a first source-to-drain pitch;
• a second semiconductor die with an integrated second transistor having a second source-to-drain pitch, wherein the second source-to-drain pitch is smaller than the first source-to-drain pitch by at least 30 percent;
• a main amplifier circuit portion, wherein the first transistor is included in the main amplifier circuit portion;
• a first peaking amplifier circuit portion, wherein the second transistor is included in the peaking amplifier circuit portion;
• and
• an additional peaking amplifier circuit portion, the additional peaking amplifier circuit portion includes a first additional peaking amplifier circuit portion, and wherein the first additional peaking amplifier circuit portion includes a third semiconductor die with an integrated third transistor having a third source-to-drain pitch.

A Doherty amplifier system comprising:

• a first semiconductor die with an integrated first transistor for a main amplifier, wherein the first semiconductor die has a first physical die area to total gate periphery ratio;
• a second semiconductor die with an integrated second transistor for a peaking amplifier, wherein the second semiconductor die has a second physical die area to total gate periphery ratio;
• and
• wherein the second physical die area to total gate periphery ratio is smaller than the first physical die area to total gate periphery ratio by at least 30 percent;
• wherein the second transistor is formed at least in part by way of a first plurality of drain contacts, a second plurality of gate contacts, and a third plurality of source contacts that extend substantially parallel with one another at least part of a distance between a drain pad and a gate pad, and wherein a source via is positioned between the drain pad and the gate pad, and is coupled at least indirectly with the source contacts of the third plurality.

A method of implementing a power amplifier, the method comprising:

• providing a first semiconductor die that includes an integrated first transistor for a main amplifier circuit, wherein the first semiconductor die has a first physical die area to total gate periphery ratio and a first source-to-drain pitch;
• providing a second semiconductor die that includes an integrated second transistor for a peaking amplifier circuit, wherein the second semiconductor die has a second physical die area to total gate periphery ratio and a second source-to-drain pitch;
• electrically coupling the first transistor to a first gate lead and a first drain lead by way of a plurality of first wire bonds and a plurality of second wire bonds;
• and
• electrically coupling the second transistor to a second gate lead and a second drain lead by way of a plurality of third wire bonds and a plurality of fourth wire bonds, wherein either (a) the second physical die area to total gate periphery ratio is smaller than the first physical die area to total gate periphery ratio by at least 30 percent, or (b) the second source-to-drain pitch is smaller than the first source-to-drain pitch by at least 30 percent,
• wherein the second semiconductor die includes a source via to which is electrically coupled a plurality of source contacts.