Hysteresis timing scheme for mode transition in a buck boost converter

A converter, comprising:

• a buck boost converter circuit configured to generate an output voltage in response to an input voltage, the buck boost converter circuit comprising:
• an upper buck transistor coupled to an input voltage node, the input voltage node configured to receive the input voltage;
• an upper boost transistor coupled to an output voltage node, the output voltage node configured to output the output voltage;
• and
• an inductor coupled between the upper buck transistor and the upper boost transistor;
• and
• a mode control logic circuit configured to generate a mode control signal to control an operation mode of the buck boost converter circuit to operate in one of a buck mode, a boost mode, and a buck-boost mode,
• wherein the mode control signal is generated based on a first duty cycle of the upper buck transistor and a second duty cycle of the upper boost transistor, and
• wherein the mode control logic circuit is configured to compare the first duty cycle of the upper buck transistor with a first transition time duty cycle when the buck boost converter circuit is operating in the buck mode.

A method of driving a converter, the converter comprising:

• a buck boost converter circuit configured to generate an output voltage in response to an input voltage, the buck boost converter circuit comprising:
• an upper buck transistor coupled to an input voltage node, the input voltage node configured to receive the input voltage;
• an upper boost transistor coupled to an output voltage node, the output voltage node configured to output the output voltage;
• and
• an inductor coupled between the upper buck transistor and the upper boost transistor;
• and
• a mode control logic circuit configured to generate a mode control signal to control an operation mode of the buck boost converter circuit to operate in one of a buck mode, a boost mode, and a buck-boost mode;
• the method comprising:
• comparing, by the mode control logic circuit, a first duty cycle of the upper buck transistor with a first transition time duty cycle when the buck boost converter circuit is operating in the buck mode;
• comparing, by the mode control logic circuit, a second duty cycle of the upper boost transistor with the first transition time duty cycle when the buck boost converter circuit is operating in the boost mode;
• and
• comparing, by the mode control logic circuit, the first duty cycle of the upper buck transistor and the second duty cycle of the upper boost transistor with a second transition time duty cycle when the buck boost converter circuit is operating in the buck-boost mode, the second transition time duty cycle being less than the first transition time duty cycle.