Performance sensitive series string power supply

A method for actively controlling power in a series string load element based on the computational performance of the load element, the method comprising:

• providing data and power by default to a number of processor cores in the load element that perform computations;
• and
• dynamically managing the power supplied to and the operations performed by the processor cores using a local controller, to increase error-free computational throughput while reducing power consumption, by:
• controlling a number of voltage regulation modules (VRMs) that provide a number of power supply voltages to the processor cores;
• testing performance of at least one of the processor cores by providing specific input data and comparing an actual computational output from the processor core to a provided expected computational output to determine that the expected computational output is produced within an allotted time span;
• and
• repeating the tests by adding selected input data propagation delays to estimate a maximum tolerable delay for the processor core being tested.

A computer program product, comprising a non-transitory hardware storage medium containing instructions that, when executed by a processor, cause the processor to perform operations comprising:

• providing data and power by default to a number of processor cores in the load element that perform computations;
• and
• dynamically managing the power supplied to and the operations performed by the processor cores to increase error-free computational throughput while reducing power consumption, by:
• controlling a number of voltage regulation modules (VRMs) provide a number of power supply voltages to the processor cores;
• testing performance of at least one of the processor cores by providing specific input data and comparing an actual computational output from the processor core to a provided expected computational output to determine that the expected computational output is produced within an allotted time span;
• and
• repeating the tests for selected added input data propagation delays to estimate a maximum tolerable delay for the processor core being tested.

A system for actively controlling power in a series string load element based on the computational performance of the load element, the system comprising:

• means for providing data and power by default to a number of processor cores in the load element that perform computations;
• and
• means for dynamically managing the power supplied to and the operations performed by the processor cores to increase error-free computational throughput while reducing power consumption, by:
• controlling a number of voltage regulation modules (VRMs) that provide a number of power supply voltages to the processor cores;
• testing performance of at least one of the processor cores by providing specific input data and comparing an actual computational output from the processor core to a provided expected computational output to determine that the expected computational output is produced within an allotted time span, and
• repeating the tests for selected added input data propagation delays to estimate a maximum tolerable delay for the processor core being tested.