PFM efficiency optimizer for fast load transient response
AssigneeDialog Semiconductor (UK) Limited
InventorNuno Miguel Nogueira Dias
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Abstract
A method for pulse-frequency modulation efficiency optimization, for fast load transient response, in a DC-DC switching converter, is disclosed. The method provides for dynamic blanking, of the under voltage comparator, while maintaining the maximum switching frequency in pulse-frequency mode. The optimization becomes more relevant with the reduction of the regulated output voltage. A further object of the disclosure is to increase the power conversion efficiency of pulse-frequency mode (PFM) by increasing the Load Bursting Point (LBP), maintaining compatibility with the fast load transient response of current DC-DC switching converter architectures.
Claims20
A DC-DC current-control mode switching converter, comprising:
- an under voltage comparator, configured to detect an output voltage drop, wherein said under voltage comparator receives said switching converter output voltage on a non-inverting input, and a reference voltage on an inverting input;
- a modulator and logic circuit, configured to indicate a load is above a defined high point, and configured to bring an inductor current back into regulation;
- a delay generator, connected between said modulator and logic circuit and said under voltage comparator, wherein said delay generator is configured to receive a randomized sum of reset times from each phase of said switching converter, and to delay said under voltage comparator dependent on load conditions of said switching converter,
- wherein during a pulse-frequency modulation (PFM) mode and low loads, a first reset time is used, and during the PFM mode at higher loads, a second reset time is used, wherein said second reset time is less than said first reset time.
A method for pulse-frequency modulation efficiency optimization, for fast load transient response, in a current-control mode DC-DC switching converter, comprising the steps of:
- providing an under voltage comparator, wherein said under voltage comparator receives said switching converter output voltage on a non-inverting input, and a reference voltage on an inverting input, to detect an output voltage drop;
- providing a modulator and logic circuit, to indicate a load is above a defined high point, and to bring an inductor current back into regulation;
- providing a delay generator, to receive a randomized sum of reset times from each phase of said switching converter, and to delay said under voltage comparator dependent on load conditions of said switching converter,
- wherein during a pulse-frequency modulation (PFM) mode and low loads a first reset time is used, and during the PFM mode at higher loads a second reset time is used, wherein said second reset time is less than said first reset time;
- and
- increasing power conversion efficiency, for both single phase and multi-phase operation of said switching converter.
Dependencies are inferred from the claim text.