Self-aligned 3D memory with confined cell

A memory, comprising:

• a plurality of first conductors in a first conductor layer having sidewalls extending in a first direction, and a plurality of second conductors in a second conductor layer having sidewalls extending in a second direction and crossing over the plurality of first conductors at cross-points;
• and
• an array of memory cell stacks disposed in the cross-points between the first conductors and the second conductors, each memory cell stack in a corresponding cross-point in the array comprising:
• an ovonic threshold switch, a conductive barrier layer, and a memory cell in series, and having a first pair of opposing sides aligned with the sidewalls of the first conductor at the corresponding cross-point, and a layer of insulating material on a second pair of opposing sides aligned with the sidewalls of the second conductor at the corresponding cross-point, the memory cell including insulating spacers on the first pair of opposing sides and a body of phase change memory material confined between the spacers, the spacers having outside surfaces aligned with sidewalls of the first conductor at the corresponding cross-point;
• and
• a layer of the phase change memory material lining the second conductors in the plurality of second conductors, and in contact with the bodies of phase change memory material in the memory cell stacks, and separating the bodies of phase change memory material from the second conductors at the corresponding cross-point.

A method of manufacturing an integrated circuit, comprising:

• forming a plurality of first conductors in a first conductor layer having sidewalls extending in a first direction, and a plurality of second conductors in a second conductor layer having sidewalls extending in a second direction and crossing over the plurality of first conductors at cross-points having cross-point areas defined by widths of the first and second conductors;
• and
• forming an array of memory cell stacks disposed in the cross-points between the first conductors and the second conductors, each memory cell stack in a corresponding cross-point in the array comprising:
• a switch element, a conductive barrier layer, and a memory cell in series, and having sides aligned within the cross-point area of the corresponding cross-point, the memory cell including confinement spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the spacers;
• and
• forming a layer of the programmable resistance memory material lining the second conductors in the plurality of second conductors, and in contact with the bodies of programmable resistance memory material in the memory cell stacks, and separating the bodies of programmable resistance memory material from the second conductors at the corresponding cross-point.