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US 10,593,874 B2Granted
Variable resistance memory devices and methods of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKyu-Rie Sim, Dae-Hwan Kang, Gwan-Hyeob Koh
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Abstract
A variable resistance memory device includes first memory cells and second memory cells. The first memory cells are between first and second conductive lines, and at areas at which the first and second conductive lines overlap. The second memory cells are between the second and third conductive lines, and at areas at which the second and third conductive lines overlap. Each first memory cell includes a first variable resistance pattern and a first selection pattern. Each second memory cell includes a second variable resistance pattern and a second selection pattern. At least one of the second memory cells is shifted from a closest one of the first memory cells.
Claims17
A variable resistance memory device, comprising:
- first conductive lines arranged in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, and the first and second directions being parallel to an upper surface of the substrate;
- second conductive lines arranged in the second direction on the first conductive lines, each of the second conductive lines extending in the first direction;
- third conductive lines arranged in the first direction on the second conductive lines, each of the third conductive lines extending in the second direction;
- first memory cells between the first and second conductive lines, the first memory cells at respective cross areas of the first conductive lines and the second conductive lines in a third direction, the third direction substantially perpendicular to the upper surface of the substrate, and each of the first memory cells including a first variable resistance pattern, a first selection pattern over the first variable resistance pattern and a first intermediate electrode between the first selection pattern and the first variable resistance pattern;
- and
- second memory cells between the second and third conductive lines, the second memory cells at respective cross areas of the second conductive lines and the third conductive lines in the third direction, and each of the second memory cells including a second variable resistance pattern, a second selection pattern over the second variable resistance pattern and a second intermediate electrode between the second selection pattern and the second variable resistance pattern;
- a first spacer on a sidewall of each of the first and the second variable resistance patterns;
- and
- a second spacer on a sidewall of the first and the second selection patterns,
- wherein at least one of the second memory cells is shifted from a closest one of the first memory cells in the first direction or in the second direction in a plan view wherein the first and second variable resistance patterns include any one of GST, super lattice having germanium-tellurium and antimony-tellurium, IST, and BST, and
- wherein the first and second selection patterns include an ovonic threshold switch (OTS) material.
8 more elements
A variable resistance memory device, comprising:
- first conductive lines arranged in a first direction on a substrate, each of the first conductive lines extending in a second direction crossing the first direction, the first and second directions being parallel to an upper surface of the substrate;
- second conductive lines arranged in the second direction on the first conductive lines, each of the second conductive lines extending in the first direction;
- third conductive lines arranged in the first direction on the second conductive lines, each of the third conductive lines extending in the second direction;
- first memory cells between the first and second conductive lines, the first memory cells at respective cross areas of the first conductive lines and the second conductive lines in a third direction, the third direction substantially perpendicular to the upper surface of the substrate, each of the first memory cells including a first variable resistance pattern, a first selection pattern over the first variable resistance pattern, and a first intermediate electrode between the first selection pattern and the first variable resistance pattern;
- and
- second memory cells between the second and third conductive lines, the second memory cells at respective cross areas of the second conductive lines and the third conductive lines in the third direction, each of the second memory cells including a second variable resistance pattern, a second selection pattern over the second variable resistance pattern and a second intermediate electrode between the second selection pattern and the second variable resistance pattern;
- a first spacer on a sidewall of each of the first and the second variable resistance patterns;
- and
- a second spacer on a sidewall of the first and the second selection patterns,
- wherein the second memory cells do not overlap the first memory cells, respectively, in the third direction,
- wherein the first and second variable resistance patterns include any one of GST, super lattice having germanium-tellurium and antimony-tellurium, IST, and BST, and
- wherein the first and second selection patterns include an ovonic threshold switch (OTS) material.
9 more elements
Dependencies are inferred from the claim text.