US 10,593,803 B2 · Self-aligned shallow trench isolation and doping for vertical fin transistors

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

Claims20

Dependent claims

A semiconductor device structure comprising:

a first set of two or more collinear vertical fin segments on a substrate, wherein the collinear vertical fin segments of the first set are separated from each other by a fin trench;
a second set of two or more collinear vertical fin segments on the substrate adjacent to the first set of two or more collinear vertical fin segments;
and
a third set of two or more collinear vertical fin segments on the substrate adjacent to the second set of two or more collinear vertical fin segments, wherein the third set of two or more collinear vertical fin segments is separated from the second set of two or more collinear vertical fin segments by a fin gap with a distance greater than the distance between at least one vertical fin segment of the first set and at least one vertical fin segment of the second set.

1 more element

A semiconductor device structure comprising:

a first set of two or more collinear vertical fin segments on a substrate, wherein the collinear vertical fin segments of the first set are separated from each other by a fin trench;
a second set of two or more collinear vertical fin segments on the substrate adjacent to the first set of two or more collinear vertical fin segments;
a third set of two or more collinear vertical fin segments on the substrate adjacent to the second set of two or more collinear vertical fin segments, wherein the third set of two or more collinear vertical fin segments is separated from the second set of two or more collinear vertical fin segments by a fin gap with a distance greater than the distance between at least one vertical fin segment of the first set and at least one vertical fin segment of the second set;
and
a fourth set of two or more collinear vertical fin segments on the substrate adjacent to the third set of two or more collinear vertical fin segments.

2 more elements

Dependencies are inferred from the claim text.

Self-aligned shallow trench isolation and doping for vertical fin transistors

Life of this patent

Self-aligned shallow trench isolation and doping for vertical fin transistors

Life of this patent

Abstract

Claims20