Semiconductor devices and methods of fabricating the same

A method of fabricating a semiconductor device, the method comprising:

• forming a trench in a substrate to form an active pattern;
• forming a first liner layer extending on the active pattern;
• forming a field isolation layer on the first liner layer;
• forming a field isolation pattern and a first liner pattern by etching the field isolation layer and the first liner layer, respectively, wherein etching the field isolation layer and the first liner layer comprises exposing an upper portion, including an uppermost surface, of the active pattern underlying the first liner layer and forming the first liner pattern on a lower portion of the active pattern, and wherein the upper portion of the active pattern is exposed by the field isolation pattern;
• after forming the field isolation pattern and the first liner pattern, forming a second liner pattern and a spacer pattern on the active pattern, the spacer pattern overlapping the second liner pattern;
• forming a source/drain pattern on the active pattern adjacent the spacer pattern;
• forming a gate insulating pattern on the upper portion of the active pattern;
• and
• forming a gate pattern on the gate insulating pattern and crossing the active pattern, the spacer pattern being on a sidewall of the gate pattern,
• wherein the second liner pattern includes a high-k dielectric material,
• wherein the second liner pattern is self-aligned with the spacer pattern, and
• wherein the source/drain pattern directly contacts both the spacer pattern and the second liner pattern and has a germanium content greater than a germanium content of the active pattern.

A method of fabricating a semiconductor device, the method comprising:

• forming an active pattern and a mask pattern sequentially stacked on a substrate, the active pattern protruding from the substrate, and the mask pattern overlapping an uppermost surface of the active pattern;
• forming a first liner layer on the active pattern and the mask pattern;
• forming a field isolation layer on the first liner layer;
• etching the field isolation layer, the first liner layer, and the mask pattern to form a field isolation pattern and a first liner pattern, respectively, and to expose an upper portion, including the uppermost surface, of the active pattern, wherein the field isolation pattern and the first liner pattern are on a side of a lower portion of the active pattern, and wherein the field isolation pattern is formed concurrently with the first liner pattern or before the first liner pattern is formed;
• forming a second liner layer on the upper portion of the active pattern after forming the field isolation pattern and the first liner pattern;
• forming a dummy gate on the second liner layer, the dummy gate crossing the active pattern;
• forming spacer patterns on opposing sidewalls of the dummy gate, respectively, and on the second liner layer;
• forming a source/drain pattern on the active pattern adjacent one of the spacer patterns;
• and
• replacing the dummy gate with a gate pattern,
• wherein the source/drain pattern is disposed on a sidewall of the second liner layer and an outer-sidewall of the one of the spacer patterns.