Vertical transistor with one atomic layer gate length
AssigneeInternational Business Machines Corporation
InventorsJianshi Tang, Qing Cao
Life of this patent
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Abstract
A vertical transistor and a method of creating the same are provided. The vertical transistor has a substrate and a gate comprising a two-dimensional (2D) material on top of the substrate. There is a spacer on top of the gate. There is a gate dielectric comprising (i) a first portion on top of the spacer, (ii) a second portion extending down to a first side surface of the spacer and a side surface of the gate, and (iii) a third portion on top of the substrate. There is a channel comprising three portions. There is a first electrode on top of the first portion of the channel and a second electrode on top of the third portion of the channel.
Claims19
A vertical transistor, comprising:
- a substrate;
- a gate comprising a two-dimensional (2D) material on top of the substrate;
- a spacer on top of the gate;
- a gate dielectric comprising (i) a first portion on top of the spacer, (ii) a second portion extending down to a first side surface of the spacer and a side surface of the gate, and (iii) a third portion on top of the substrate;
- a channel comprising (i) a first portion on top of the first portion of the gate dielectric, (ii) a second portion extending down to a first side surface of the second portion of the gate dielectric, and (iii) a third portion on top of the third portion of the gate dielectric;
- a mask layer between the first portion of the gate dielectric and the spacer;
- a first electrode on top of the first portion of the channel;
- and
- a second electrode on top of the third portion of the channel.
A vertical transistor, comprising:
- a substrate;
- a gate comprising a two-dimensional (2D) material on top of the substrate;
- a spacer on top of the gate;
- a gate dielectric comprising (i) a first portion on top of the spacer, (ii) a second portion extending down to a first side surface of the spacer and a side surface of the gate, and (iii) a third portion on top of the substrate;
- a channel comprising (i) a first portion on top of the first portion of the gate dielectric, (ii) a second portion extending down to a first side surface of the second portion of the gate dielectric, and (iii) a third portion on top of the third portion of the gate dielectric;
- a first electrode on top of the first portion of the channel;
- and
- a second electrode on top of the third portion of the channel, wherein a left side surface of the second electrode is not in contact with a right side surface of the second portion of the channel.
A method of fabricating a vertical transistor, comprising:
- providing a substrate;
- defining a first spacer on top of the substrate;
- depositing a gate comprising a two-dimensional (2D) material on top of the first spacer;
- defining a second spacer on top of the gate;
- forming a mask on top of the second spacer;
- removing the second spacer, the gate, and the first spacer from areas not protected by the mask;
- depositing a gate dielectric comprising:
- (i) a first portion on top of the second spacer, (ii) a second portion comprising a first side surface of the second spacer, a first side surface of the gate, and a first side surface of the first spacer, and (iii) a third portion on top of the substrate;
- depositing a channel comprising:
- (i) a first portion on top of the first portion of the gate dielectric, (ii) a second portion comprising a first side surface of the second portion of the gate dielectric, and (iii) a third portion on top of the third portion of the gate dielectric;
- forming a first electrode on top of the first portion of the channel;
- and
- forming a second electrode on top of the third portion of the channel.
A method of fabricating a vertical transistor, comprising:
- providing an insulating substrate;
- depositing a gate comprising a two-dimensional (2D) material on top of the substrate;
- defining a spacer on top of the gate;
- forming a mask on top of the spacer;
- removing the spacer and the gate from areas not protected by the mask;
- depositing a gate dielectric comprising:
- (i) a first portion on top of the spacer, (ii) a second portion comprising a first side surface of the spacer and a first side surface of the gate, and (iii) a third portion on top of the substrate;
- depositing a channel comprising:
- (i) a first portion on top of the first portion of the gate dielectric, (ii) a second portion comprising a first side surface of the second portion of the gate dielectric, and (iii) a third portion on top of the third portion of the gate dielectric;
- forming a first electrode on top of the first portion of the channel;
- and
- forming a second electrode on top of the third portion of the channel.
Dependencies are inferred from the claim text.