Back to results
US 10,593,780 B2Granted
Forming replacement low-K spacer in tight pitch fin field effect transistors
AssigneesInternational Business Machines Corporation, Globalfoundries Inc., STMicroelectronics S.r.l.
InventorsXiuyu Cai, Chun-Chen Yeh, Qing Liu, Ruilong Xie
Life of this patent
Estimating the term…
Abstract
A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
Claims17
A semiconductor device comprising:
- a gate structure comprising at least a gate electrode present on a channel region of a fin structure;
- and
- a composite spacer present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a solid dielectric with a second dielectric constant that is less than the first dielectric constant, the lower portion having an upper surface that is entirely in contact with a base surface of the upper portion to provide that the upper portion covers the lower portion, and an etch barrier layer between sidewalls of the upper and lower portion of the composite spacer and the gate structure, the etch barrier layer having a U-shape geometry in which the lower portion of the composite spacer is encapsulated between the etch barrier layer and the upper portion of the composite spacer, wherein the etch barrier layer comprises at least one of silicon, boron, nitrogen and carbon, and the etch barrier layer on at least one side of the composite spacer has a portion on an outer sidewall of the lower portion of the composite spacer, and the etch barrier layer has a portion on an inner sidewall of the lower portion of the composite spacer that is contiguous with a portion of the etch barrier layer on an inner sidewall of the upper portion of the composite spacer, wherein the etch barrier layer is not present on an outer sidewall of the upper portion of the composite spacer, wherein the portion of the etch barrier layer on the inner sidewall of the lower portion of the composite spacer is entirely in contact with the lower portion of the composite spacer, and an entirety of the gate electrode is in contact with the portion of the etch barrier layer on the inner sidewall of the lower portion of the composite spacer.
A semiconductor device comprising:
- a gate structure including at least a gate electrode;
- and
- a composite spacer present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion of a solid dielectric having a second dielectric constant that is less than the first dielectric constant, the lower portion having an upper surface that is entirely in contact with a base surface of the upper portion to provide that the upper portion covers the lower portion, and an etch barrier layer between sidewalls of the upper and lower portion of the composite spacer and the gate structure, the etch barrier layer having a U-shape geometry in which the lower portion of the composite spacer is encapsulated between the etch barrier layer and the upper portion of the composite spacer, wherein the etch barrier layer comprises at least one of silicon, boron, nitrogen and carbon, and the etch barrier layer on at least one side of the composite spacer has a portion on an outer sidewall of the lower portion of the composite, and the etch barrier layer has a portion on an inner sidewall of the lower portion of the composite spacer that is contiguous with a portion on the etch barrier layer on an inner sidewall of the upper portion of the composite spacer, wherein the etch barrier layer is not present on an outer sidewall of the upper portion of the composite spacer, wherein the portion of the etch barrier layer on the inner sidewall of the lower portion of the composite spacer is entirely in contact with the lower portion of the composite spacer, and an entirety of the gate electrode is in contact with the portion of the etch barrier layer on the inner sidewall of the lower portion of the composite spacer.
A semiconductor device comprising:
- a gate structure including at least a gate electrode present on a channel region of a fin structure;
- and
- a composite spacer present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion of a solid dielectric having a second dielectric constant that is less than the first dielectric constant, the lower portion having an upper surface that is entirely in contact with a base surface of the upper portion to provide that the upper portion covers the lower portion, and an etch barrier layer between sidewalls of the upper and lower portion of the composite spacer and the gate structure, the etch barrier layer having a U-shape geometry in which the lower portion of the composite spacer is encapsulated between the etch barrier layer and the upper portion of the composite spacer, wherein the lower portion having the second dielectric constant comprises a dielectric selected from the group consisting of silicon carbon boron nitride (SiCBN), silicon oxycarbonitride (SiOCN), fluorine doped silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, porous carbon doped silicon dioxide, organosilicate glass (OSG), diamond-like carbon (DLC) and combinations thereof, and the etch barrier layer on at least one side of the composite spacer has a portion on an outer sidewall of the lower portion of the composite spacer, and the etch barrier layer has a portion on an inner sidewall of the lower portion of the composite spacer that is contiguous with a portion of the etch barrier layer on an inner sidewall of the upper portion of the composite spacer, wherein the etch barrier layer is not present on an outer sidewall of the upper portion of the composite spacer, wherein the portion of the etch barrier layer on the inner sidewall of the lower portion of the composite spacer is entirely in contact with the lower portion of the composite spacer, and an entirety of the gate electrode is in contact with the portion of the etch barrier layer on the inner sidewall of the lower portion of the composite spacer.
Dependencies are inferred from the claim text.