Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device including a field effect transistor (FET), the method comprising:

• forming a first fin and a second fin by patterning a substrate;
• forming a first insulating layer over the substrate so that upper portions of the first and second fins project from the first insulating layer;
• forming a dummy gate structure over the projecting first and second fins;
• forming a first dummy epitaxial semiconductor layer and a second dummy epitaxial semiconductor layer on the first fin and the second fin, respectively;
• forming an dielectric layer to cover the first and second dummy epitaxial semiconductor layers;
• recessing the first and second dummy epitaxial semiconductor layers and the first and second fins, thereby forming a first opening and a second opening in the dielectric layer;
• forming a first epitaxial semiconductor layer and a second epitaxial semiconductor layer on the first recessed fin in the first opening and on the second recessed fin in the second opening, respectively;
• forming an alloy layer over the first and second epitaxial semiconductor layers, wherein:
• the first epitaxial semiconductor layer and the second epitaxial semiconductor layer are in contact with and connected by the alloy layer, and the first epitaxial semiconductor layer is not in direct contact with the second epitaxial semiconductor layer, and
• the alloy layer wraps around the first and second epitaxial semiconductor layers.

A semiconductor device including a p-type field effect transistor (FET) and an n-type FET, at least one of the p-type FET and the n-type FET comprising:

• a first channel, a first source and a first drain;
• a second channel, a second source and a second drain;
• and
• a gate structure disposed over the first and second channels, the gate structure including a gate dielectric layer and a gate electrode layer, wherein:
• the first source includes a first epitaxial semiconductor layer disposed over a first bottom fin and the second source includes a second epitaxial semiconductor layer disposed over a second bottom fin,
• the first source and the second source are in contact with and connected by a metal alloy layer,
• one or more voids are formed in and surrounded by the alloy layer, and
• the first epitaxial semiconductor layer is not in direct contact with the second epitaxial semiconductor layer.