LDMOS with high-k drain STI dielectric
AssigneeTexas Instruments Incorporated
InventorsUmamaheswari Aghoram, Pushpa Mahalingam, Alexei Sadovnikov, Eugene C Davis
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Abstract
A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure is formed between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon dioxide.
Claims20
A method of fabricating a laterally diffused metal oxide silicon (LDMOS) transistor in a first region of a wafer, the method comprising:
- providing a wafer for which locations for a source region, a drain contact region and a gate region have been defined and having an extended drain region formed in the wafer;
- forming a first shallow trench isolation (STI) structure in the first region and filling the first STI structure with a first dielectric material;
- forming a drain STI structure in the extended drain region of the LDMOS transistor and filling the drain STI structure with a second dielectric material that is different from the first dielectric material and that comprises a high-k dielectric;
- and
- forming a double-diffused well (DWELL) and a drain contact, such that the drain STI structure extends from the DWELL to the drain contact.
A method of fabricating an integrated circuit, comprising:
- forming, within a semiconductor substrate having a first conductivity type, a well region having a second different conductivity type;
- forming within the well region a first isolation structure filled with a first dielectric material having a first dielectric constant;
- and
- forming within the well region a second isolation structure filled with a second dielectric material having a second different dielectric constant;
- and
- forming a gate electrode over the second isolation structure,
- wherein the second isolation structure extends from a double-diffused well (DWELL) to a drain contact formed within the well region.
A method of fabricating an integrated circuit, comprising:
- forming, within a semiconductor substrate having a first conductivity type, a well region having a second different conductivity type;
- forming within the well region a first isolation structure filled with a first dielectric material having a first dielectric constant;
- and
- forming within the well region a second isolation structure filled with a second dielectric material having a second different dielectric constant;
- and
- forming a double-diffused well (DWELL) adjacent the well region, the second isolation structure forming a lateral boundary of the DWELL at a surface of the semiconductor substrate.
Dependencies are inferred from the claim text.