Field plate structure for power semiconductor device and manufacturing method thereof
OwnerChun Wai Ng, Iftikhar Ahmed +1inventors
InventorsChun Wai Ng, Iftikhar Ahmed, Johnny Kin On Sin
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Abstract
A structure and a manufacturing method of a power semiconductor device are provided. A structure of thin semi-insulating field plates (32, 33, 34) located between metal electrodes (21, 22, 23) at the surface of the power semiconductor device is provided. The thin semi-insulating field plates (32, 33, 34) are formed by depositing before metallization and annealing after the metallization. The present invention can be used in lateral power semiconductor devices and vertical power semiconductor devices.
Claims15
A semi-insulating field plate structure, comprising:
- a semi-insulating layer on a silicon oxide layer and between metal electrodes on a surface of a power semiconductor device,
- wherein the semi-insulating layer contains at least one resistivity material selected from titanium nitride and amorphous silicon,
- the semi-insulating layer has a thickness of about 5 nm to 100 nm and a resistivity of about 100 ohm-cm to 10,000 ohm-cm, and
- the semi-insulating layer and the silicon oxide layer are in direct contact with a side of each of the metal electrodes, wherein the side is where the metal electrodes face each other,
- the metal electrodes directly overlap with the silicon oxide layer.
A method for manufacturing a semi-insulating field plate structure, comprising:
- patterning silicon oxide that directly covers a silicon surface of a device wafer to form contact holes;
- depositing a thin semi-insulating layer directly on the entire surface of the wafer and the silicon oxide;
- depositing and patterning metal electrodes directly on the thin semi-insulating layer;
- and
- annealing the metal electrodes and the thin semi-insulating layer,
- wherein the semi-insulating field plate structure include a semi-insulating layer on silicon oxide and between metal electrodes on a surface of a power semiconductor device,
- wherein the semi-insulating layer has a thickness of about 5 nm to 100 nm and a resistivity of about 100 ohm-cm to 10,000 ohm-cm.
A method for manufacturing a semi-insulating field plate structure, comprising:
- patterning silicon oxide that directly covers a silicon surface of a side of a device wafer and forming contact holes;
- depositing a thin semi-insulating layer on the entire surface of the side of the device wafer;
- depositing and patterning metal electrodes directly on the thin semi-insulating layer and at the contact holes;
- and
- annealing the semi-insulating field plate structure,
- wherein semi-insulating field plate structure include a semi-insulating layer on silicon oxide and between metal electrodes on a surface of a power semiconductor device,
- wherein the semi-insulating layer contains titanium nitride.
Dependencies are inferred from the claim text.