Method for making a semiconductor device having reduced contact resistance

A method for making a semiconductor device comprising:

• forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, the source region comprising a lower source region and an upper source region divided by a source dopant diffusion blocking superlattice with the upper source region having a same conductivity and higher dopant concentration than the lower source region, and the drain region comprising a lower drain region and an upper drain region divided by a drain dopant diffusion blocking superlattice with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region, each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, with the upper drain region and upper source region being level with an upper surface of the semiconductor layer;
• forming a gate on the channel region;
• depositing at least one metal layer on the source and drain contact regions to define respective source and drain contacts;
• and
• applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form respective source and drain contact insulating interfaces between the upper source and drain regions and adjacent portions of the at least one metal layer.

A method for making a semiconductor device comprising:

• forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, the source region comprising a lower source region and an upper source region divided by a source dopant diffusion blocking superlattice with the upper source region having a same conductivity and higher dopant concentration than the lower source region, and the drain region comprising a lower drain region and an upper drain region divided by a drain dopant diffusion blocking superlattice with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region, each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
• the upper drain region and upper source region being raised above an upper surface of the semiconductor layer;
• forming a gate on the channel region;
• depositing at least one metal layer on the source and drain contact regions to define respective source and drain contacts;
• and
• applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form respective source and drain contact insulating interfaces between the upper source and drain regions and adjacent portions of the at least one metal layer.