Integrated circuits having converted self-aligned epitaxial etch stop
AssigneeGlobalfoundries Inc.
InventorsJiehui Shu, Ruilong Xie, Hui Zang, Haiting Wang
Life of this patent
Estimating the term…
Abstract
Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.
Claims17
An integrated circuit structure comprising:
- complementary transistors on a first layer;
- an isolation structure between the complementary transistors, wherein each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and wherein insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors;
- a horizontal spacer extending parallel to the first layer from the isolation structure to the source/drain regions;
- and
- an etch stop layer extending from the insulating spacers and extending along the source/drain regions, wherein the etch stop layer does not extend along an entirety of the horizontal spacer.
An integrated circuit structure comprising:
- complementary transistors on a first layer, wherein the complementary transistors comprise one N-type field effect transistor (NFET) and one P-type field effect transistor (PFET);
- an isolation fin between the complementary transistors, wherein each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, wherein the source/drain regions in the NFET are different from the source/drain regions in the PFET, and wherein insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors;
- a horizontal spacer extending parallel to the first layer from the isolation fin to the source/drain regions;
- and
- an etch stop layer extending from the insulating spacers and extending along the source/drain regions, wherein the etch stop layer does not extend along an entirety of the horizontal spacer.
An integrated circuit structure comprising:
- complementary transistors on a first layer;
- an isolation structure between the complementary transistors, wherein each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, wherein first insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors, and wherein the isolation structure includes an isolation fin parallel to the gate conductors;
- second insulating spacers on the isolation fin, wherein the second insulating spacers include a vertical spacer along sides of the isolation fin and a horizontal spacer extending parallel to the first layer between the isolation fin and the source/drain regions;
- and
- an etch stop layer extending from and contacting the first insulating spacers and extending along the source/drain regions, wherein the etch stop layer does not extend along an entirety of the horizontal spacer.
Dependencies are inferred from the claim text.