SOI device structures with doped regions providing charge sinking
AssigneeGlobalfoundries Inc.
InventorsJagar Singh, Jerome Ciavatti, Jae Gon Lee, Josef Watts
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AssigneeGlobalfoundries Inc.
InventorsJagar Singh, Jerome Ciavatti, Jae Gon Lee, Josef Watts
Estimating the term…
Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.
A structure formed using a silicon-on-insulator wafer, the structure comprising:
A method comprising:
Dependencies are inferred from the claim text.