Vertical field effect transistor (VFET) device with controllable top spacer

A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:

• depositing a dielectric hardmask layer on a wafer;
• forming at least one fin hardmask on the dielectric hardmask layer;
• patterning the dielectric hardmask layer and the wafer using the at least one fin hardmask to form at least one fin in the wafer and a dielectric cap on the at least one fin;
• forming a bottom source and drain in the wafer at a base of the at least one fin;
• forming bottom spacers on the bottom source and drain;
• forming a gate stack alongside the at least one fin;
• burying the at least one fin in a dielectric fill material;
• selectively removing the at least one fin hardmask;
• recessing the gate stack to form a cavity in the dielectric fill material at a top of the at least one fin;
• depositing a spacer material into the cavity;
• recessing the spacer material to form top spacers on the gate stack;
• removing the dielectric cap;
• and
• forming a top source and drain at a top of the at least one fin.