Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof

A method of preparing a multilayer structure, the method comprising:

• depositing a handle dielectric layer comprising a flowable insulating layer on a front surface of a single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the flowable insulating layer comprises a flowable silazane;
• curing the flowable insulating layer by annealing the flowable insulating layer at a temperature between about 800° C. and about 1000° C.;
• and
• bonding a donor dielectric layer on a front surface of a single crystal semiconductor donor substrate to the handle dielectric layer comprising the flowable insulating layer to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, a central plane between the front and back surfaces of the semiconductor donor substrate, and a bulk region between the front and back surfaces of the semiconductor donor substrate, and further wherein the single crystal semiconductor donor substrate comprises a cleave plane.

A multilayer structure comprising:

• a single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front surface and the back surface of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate;
• a handle dielectric layer comprising a flowable insulating layer comprising a flowable silazane or a reflowable insulating layer comprising a silicate glass selected from the group consisting of phosphosilicate glass, borosilicate glass, borophosphosilicate glass, and any combination thereof, the handle dielectric layer being in interfacial contact with the front surface of the single crystal semiconductor handle substrate;
• a donor dielectric layer in interfacial contact with the handle dielectric layer;
• and
• a single crystal semiconductor device layer.