Semiconductor device including a gate pitch and an interconnection line pitch and a method for manufacturing the same
AssigneesSamsung Electronics Co., Ltd., Korea Advance Institute of Science and Technology
InventorsJae-Woo Seo, Youngsoo Shin
Life of this patent
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Abstract
A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.
Claims12
A semiconductor device comprising:
- a first logic cell and a second logic cell on a substrate,
- wherein a structure of a logic circuit of the first logic cell is the same as a structure of a logic circuit of the second logic cell,
- wherein each of the first and second logic cells comprises:
- a gate electrode intersecting a PMOSFET region and an NMOSFET region of the substrate and extending in a first direction;
- and
- an internal interconnection line disposed on the gate electrode and extending in the first direction,
- wherein the internal interconnection line is an interconnection line included in the logic circuit of each of the first and second logic cells, and
- wherein a distance by which an internal interconnection line of the first logic cell is offset from a gate electrode of the first logic cell in a plan view is different from a distance by which a corresponding internal interconnection line of the second logic cell is offset from a corresponding gate electrode of the second logic cell in a plan view.
A semiconductor device comprising:
- a first logic cell and a second logic cell on a substrate,
- wherein a structure of a logic circuit of the first logic cell is the same as a structure of a logic circuit of the second logic cell,
- wherein each of the first and second logic cells comprises:
- a first gate electrode and a second gate electrode intersecting a PMOSFET region and an NMOSFET region of the substrate and extending in a first direction;
- and
- an internal interconnection line disposed on the first and second gate electrodes and extending in the first direction, the internal interconnection line being between the first and second gate electrodes in a plan view,
- wherein the internal interconnection line is an interconnection line included in the logic circuit of each of the first and second logic cells,
- wherein, in the first logic cell, the internal interconnection line is closer to the first gate electrode than the second gate electrode in a plan view, and
- wherein, in the second logic cell, the internal interconnection line is closer to the second gate electrode than the first gate electrode in a plan view.
Dependencies are inferred from the claim text.