Standard cell architecture with M1 layer unidirectional routing

A complementary metal oxide semiconductor (CMOS) device, comprising:

• metal oxide semiconductor transistors each having gates formed from gate interconnects, the gate interconnects extending in a first direction, and each having a source and a drain;
• metal one (M1) layer interconnects disposed on an M1 layer, the M1 layer interconnects being parallel to the gate interconnects and extending in the first direction only;
• a metal zero (M0) layer interconnect disposed on an M0 layer that extends directly over a first gate interconnect of the gate interconnects of the metal oxide semiconductor transistors, the M0 layer interconnect extending only in a second direction orthogonal to the first direction, the M0 layer interconnect being below the M1 layer and isolated from directly connecting to the first gate interconnect;
• and
• a single layer interconnect different from the M1 layer interconnects and the M0 layer interconnect, the single layer interconnect being connected to the M0 layer interconnect and being directly connected to a second gate interconnect of the gate interconnects.