Three-dimensional vertical NOR flash thin-film transistor strings

A memory structure, comprising:

• a semiconductor substrate having a substantially planar surface and including circuitry formed therein for memory circuit operation;
• an active column of semiconducting material formed above the semiconductor substrate, the active column extending along a first direction substantially orthogonal to the planar surface of semiconductor substrate and including a first heavily doped region, a second heavily doped region, and a first lightly doped region adjacent and in contact with both the first and second heavily doped regions;
• charge-trapping material adjacent the first lightly doped region;
• and
• a first set of word line conductors provided adjacent the active column, each electrically isolated from another and each extending lengthwise along a second direction that is substantially parallel the planar surface, wherein the first and second heavily doped regions of the active column, the first lightly doped region of the active column, the charge-trapping material and each the word line conductor together form a source region, a drain region, a channel region, a storage region, and a gate electrode of one of a plurality of variable-threshold thin-film transistors along a first NOR memory string, the first and second heavily doped regions forming a common local bit line and a common source region, respectively, of the first NOR memory string.