Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies

A memory array, comprising:

• a vertical stack of alternating insulative levels and wordline levels, the wordline levels having conductive terminal ends corresponding to control gate regions, and having a charge-blocking material laterally outward of the conductive terminal ends;
• the charge-blocking material being configured as segments;
• the segments of the charge-blocking material being arranged one atop another and being vertically spaced from one another by first intervening gaps, with the insulative levels being within said first intervening gaps;
• each of the segments of the charge-blocking material having a vertical edge in opposing relation to an associated conductive terminal end of an associated wordline level;
• the vertical edges of the segments of the charge-blocking material being first vertical edges;
• terminal regions of the insulative levels including projections which extend laterally outward of the first vertical edges;
• the projections having upper surfaces, lower surfaces and second vertical edges which extend between the upper and lower surfaces;
• a charge-trapping material along the first vertical edges, and wrapping partially around the projections;
• the charge-trapping material being configured as segments which are arranged one atop another, and which are vertically spaced from one another by second intervening gaps;
• a charge-tunneling material extending vertically along the stack;
• the charge-tunneling material extending along the segments of the charge-trapping material, and some of the charge-tunneling material extending into the second intervening gaps and along the second vertical edges;
• and
• a channel material extending vertically along the charge-tunneling material.

A memory array, comprising:

• a vertical stack of alternating insulative levels and wordline levels, the wordline levels having conductive terminal ends corresponding to control gate regions, and having a charge-blocking material laterally outward of the conductive terminal ends;
• the charge-blocking material being configured as segments;
• the segments of the charge-blocking material being arranged one atop another and being vertically spaced from one another by first intervening gaps;
• each of the segments of the charge-blocking material having a vertical edge in opposing relation to an associated conductive terminal end of an associated wordline level;
• the vertical edges of the segments of the charge-blocking material being first vertical edges;
• a charge-trapping material;
• the charge-trapping material being configured as segments which are arranged one atop another, and which are vertically spaced from one another by second intervening gaps;
• a charge-tunneling material extending vertically along the stack;
• the charge-tunneling material extending along the segments of the charge-trapping material;
• and
• a channel material extending vertically along the charge-tunneling material and into the second intervening gaps.

A method of forming an integrated assembly, comprising:

• forming a vertical stack of alternating first and second levels;
• the first levels comprising silicon dioxide, and the second levels comprising silicon nitride laterally capped with silicon;
• the first and second levels having exposed first and second surfaces, respectively, along an opening extending through the first and second levels;
• the first surfaces comprising the silicon dioxide, and the second surfaces comprising the silicon;
• the first surfaces comprising OH-moieties and the second surfaces substantially lacking the OH-moieties;
• coating the first surfaces with a hindering material, utilizing precursor which reacts with the OH-moieties;
• selectively forming charge-trapping material along the second surfaces relative to the coated first surfaces;
• forming charge-tunneling material extending vertically along the first and second levels, and spaced from the second levels by the charge-trapping material;
• forming channel material extending vertically along the charge-tunneling material;
• removing the silicon nitride of the second levels to leave voids;
• and
• forming conductive material within the voids.