Three-dimensional non-volatile memory device with cut off time control

A semiconductor memory device comprising:

• a stacked body including a plurality of conductive layers with an insulator interposed between adjacent pairs of conductive layers from the plurality of conductive layers, the conductive layers including a plurality of word electrode layers and at least one layer of selection gate layer provided above the word electrode layers;
• a plurality of semiconductor bodies extending in the stacked body in a stacking direction of the stacked body;
• a charge storage portion provided between one of the semiconductor bodies and one of the conductive layers;
• and
• a separation portion extending in a first direction, the separation portion separating at least the selection gate layer into a plurality of selection gates in a second direction crossing the first direction,
• the selection gates including an extract portion, a first portion, and a second portion, a distance between the extract portion and the second portion being longer than a distance between the extract portion and the first portion,
• a threshold voltage of at least one of second selection transistors being higher than a threshold voltage of at least one of first selection transistors, the first selection transistors including the semiconductor bodies disposed in the first portion as channels, the second selection transistors including the semiconductor bodies disposed in the second portion as channels.

A semiconductor memory device comprising:

• a stacked body including a plurality of conductive layers with an insulator interposed between adjacent pairs of conductive layers from the plurality of conductive layers, the conductive layers including a plurality of word electrode layers, and at least one layer of selection gate layer provided above the word electrode layers;
• a plurality of semiconductor bodies extending in the stacked body in a stacking direction of the stacked body;
• a charge storage portion provided between one of the semiconductor bodies and one of the conductive layers;
• a first separation portion extending in a first direction, the first separation portion separating the selection gate layer and the word electrode layers into a plurality of blocks in a second direction crossing the first direction;
• and
• a second separation portion extending in the first direction, and separating the selection gate layer into a first selection gate and a second selection gate in the second direction,
• a resistance of the first selection gate being different from a resistance of the second selection gate,
• a threshold voltage of a first selection transistor being different from a threshold voltage of a second selection transistor, the first selection transistor including a first semiconductor body of the semiconductor bodies as a channel, the second selection transistor including a second semiconductor body of the semiconductor bodies as a channel, the first semiconductor body being disposed in the first selection gate and the second semiconductor body being disposed in the second selection gate.