Split-gate semiconductor device with L-shaped gate

A memory array, comprising:

• a substrate;
• and
• at least two memory devices, each comprising:
• a first gate conductor disposed over a first gate dielectric structure on the substrate, wherein the first gate dielectric structure comprises a dielectric charge-trapping layer;
• a second gate conductor disposed over a second gate dielectric structure on the substrate, the second gate conductor comprising an L shape including a vertical portion adjacent to the first gate conductor and a horizontal portion on an opposite side of the vertical portion from the first gate conductor;
• and
• an inter-gate dielectric structure disposed between the first gate conductor and the second gate conductor;
• a spacer disposed on a sidewall of the horizontal portion of the second gate conductor and on a sidewall of an opposite side of the first gate conductor from the second gate conductor;
• a doped region in the substrate adjacent to the opposite side of the first gate conductor from the second gate conductor;
• a contact electrically coupled to the doped region;
• and
• an insulating material disposed over the substrate between the contact and the spacer on the sidewall of the first gate conductor,
• wherein the insulating material comprises no voids,
• wherein a first memory device and a second memory device are disposed such that the horizontal portion of the second gate conductor of the first memory device is adjacent to the horizontal portion of the second gate conductor of the second memory device.

A split gate memory cell, comprising:

• a first gate disposed over a first gate dielectric structure on a substrate, wherein the first gate dielectric structure comprises a dielectric charge-trapping layer;
• a second gate disposed over a second gate dielectric structure on the substrate, the second gate comprising an L shape including a vertical portion adjacent to the first gate and a horizontal portion on an opposite side of the vertical portion from the first gate;
• an inter-gate dielectric structure disposed between first gate and the second gate;
• a spacer disposed on a sidewall of the horizontal portion of the second gate and on a sidewall of an opposite side of the first gate from the second gate;
• and
• a doped region in the substrate adjacent to the opposite side of the first gate from the second gate;
• a contact electrically coupled to the doped region;
• and
• an insulating material disposed over the substrate between the contact and the spacer on the sidewall of the first gate, wherein the insulating material comprises no voids.