Method for producing pillar-shaped semiconductor memory device

A method for producing a pillar-shaped semiconductor memory device, the method comprising:

• a step of forming, on a substrate, a first semiconductor pillar and a second semiconductor pillar that extend in a direction perpendicular to a plane of the substrate, and that have inner insulating layers which are formed at a same height and forming semiconductor layers over and under the inner insulating layers, where the insulating layers isolate the semiconductor layers from each other, and that stand adjacent to each other;
• a step of forming a gate insulating layer so as to surround each of the first semiconductor pillar and the second semiconductor pillar;
• a step of forming a gate conductor layer so as to surround the gate insulating layer;
• a step of forming a first impurity region in a bottom portion of the first semiconductor pillar and forming a second impurity region containing an impurity having the same polarity as the first impurity region in a bottom portion of the second semiconductor pillar;
• a step of forming a third impurity region above the first impurity region and within the first semiconductor pillar, and a fourth impurity region at the same height as the third impurity region and within the second semiconductor pillar, the fourth impurity region containing an impurity having the same polarity as the third impurity region;
• a step of forming a fifth impurity region above the third impurity region and within the first semiconductor pillar, and a sixth impurity region at the same height as the fifth impurity region and within the second semiconductor pillar, the sixth impurity region containing an impurity having the same polarity as the fifth impurity region;
• a step of forming a seventh impurity region located upper than the fifth impurity region of the first semiconductor pillar and below the corresponding inner insulating layer, and an eighth impurity region at the same height as the seventh impurity region and within the second semiconductor pillar, the eighth impurity region containing an impurity having the same polarity as the seventh impurity region;
• a step of forming a ninth impurity region located upper than the corresponding inner insulating layer and within the first semiconductor pillar, and a tenth impurity region at the same height as the ninth impurity region and within the second semiconductor pillar, the tenth impurity region containing an impurity having the same polarity as the ninth impurity region;
• a step of forming an eleventh impurity region located upper than the ninth impurity region and within the first semiconductor pillar, and a twelfth impurity region at the same height as the eleventh impurity region and within the second semiconductor pillar, the twelfth impurity region containing an impurity having the same polarity as the eleventh impurity region;
• a step of forming a first wiring conductor layer surrounding a side surface of the third impurity region, a second wiring conductor layer surrounding a side surface of the fifth impurity region, a third wiring conductor layer surrounding a side surface of the fourth impurity region, and a fourth wiring conductor layer surrounding a side surface of the sixth impurity region;
• a step of forming a fifth wiring conductor layer connected to the gate conductor layer located between the fifth impurity region and the seventh impurity region, and a sixth wiring conductor layer connected to the gate conductor layer located between the sixth impurity region and the eighth impurity region at the same height as the fifth wiring conductor layer;
• a step of forming a seventh wiring conductor layer surrounding a side surface of the seventh impurity region, an eighth wiring conductor layer surrounding a side surface of the ninth impurity region and insulated from the seventh wiring conductor layer, a ninth wiring conductor layer surrounding a side surface of the eighth impurity region, and a tenth wiring conductor layer surrounding a side surface of the tenth impurity region and insulated from the ninth wiring conductor layer;
• a step of forming a twelfth wiring conductor layer connected to the gate conductor layer between the first impurity region and the third impurity region, and the fifth wiring conductor layer overlapping with the twelfth wiring conductor layer in plan view so as to extend in one direction, and forming the third wiring conductor layer, the fourth wiring conductor layer, and the tenth wiring conductor layer so as to overlap each other and extend in the one direction in plan view;
• a step of forming a thirteenth wiring conductor layer connected to the gate conductor layer between the second impurity region and the fourth impurity region, and the sixth wiring conductor layer overlapping with the thirteenth wiring conductor layer in plan view so as to extend in a direction opposite to the one direction, and forming the first wiring conductor layer, the second wiring conductor layer, and the eighth wiring conductor layer so as to overlap each other and extend in the direction opposite to the one direction in plan view;
• a step of connecting the twelfth wiring conductor layer, the fifth wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the tenth wiring conductor layer together;
• and
• a step of connecting the thirteenth wiring conductor layer, the sixth wiring conductor layer, the first wiring conductor layer, the second wiring conductor layer, and the eighth wiring conductor layer together.