Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple
AssigneeInternational Business Machines Corporation
InventorJoshua M. Rubin
Life of this patent
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Abstract
A semiconductor device includes a bottom tier including a plurality of first vertical transistors and at least one contact disposed on a first inverter gate. The device further includes a top tier including a plurality of second vertical transistors and a second inverter gate, and a monolithic inter-tier via (MIV) that lands on the at least one contact via the second inverter gate to create a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple.
Claims18
A method for fabricating a semiconductor device, comprising:
- forming a bottom tier comprising a plurality of first vertical transistors and at least one contact formed on a first inverter gate;
- forming a top tier comprising a plurality of second vertical transistors and a second inverter gate;
- and
- connecting the bottom tier to the top tier to create a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple by forming a monolithic inter-tier via (MIV) that lands on the at least one contact via the second inverter gate, and forming a ground contact from the top tier to a bottom source/drain region of the bottom tier.
A method for fabricating a semiconductor device, comprising:
- forming a bottom tier comprising a plurality of first vertical transport field-effect transistors (VTFETs) associated with a first conductivity type and at least one contact formed on a first inverter gate;
- forming a top tier comprising a plurality of second VTFETs associated with a second conductivity type and a second inverter gate;
- and
- connecting the bottom tier to the top tier to create a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple by forming a monolithic inter-tier via (MIV) that lands on the at least one contact via the second inverter gate, and forming a ground contact from the top tier to a bottom source/drain region of the bottom tier.
A semiconductor device comprising:
- a bottom tier comprising a plurality of first vertical transistors and at least one contact disposed on a first inverter gate;
- a top tier comprising a plurality of second vertical transistors and a second inverter gate;
- a monolithic inter-tier via (MIV) that lands on the at least one contact via the second inverter gate;
- and
- a ground contact connecting the top tier to a bottom source/drain region of the bottom tier;
- the MIV and the ground contact forming a three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple.
Dependencies are inferred from the claim text.