Static random access memory (SRAM) density scaling by using middle of line (MOL) flow
AssigneeInternational Business Machines Corporation
InventorsVeeraraghavan S. Basker, Kangguo Cheng, Sivananda K. Kanakasabapathy, Theodorus E. Standaert, Junli Wang
Life of this patent
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Abstract
A method is presented for forming a semiconductor structure. The method includes forming gate contacts on a semiconductor substrate, forming trench silicide (TS) contacts on the semiconductor substrate, recessing the TS contacts to form a gap region, filling the gap region of the recessed TS contacts with a dielectric, selectively etching the gate contacts to form a first conducting layer, and selectively etching the TS contacts to form a second conducting layer.
Claims18
A semiconductor structure comprising:
- a plurality of gate contacts formed on a semiconductor substrate;
- and
- a plurality of trench silicide (TS) contacts formed on the semiconductor substrate, wherein the plurality of gate contacts and the plurality of TS contacts are disposed in an alternating manner, the plurality of TS contacts recessed to form gap regions thereabove;
- wherein only the gap regions of the plurality of the recessed TS contacts are selectively filled with a dielectric, a common first conducting layer is disposed over and directly contacts a portion of each of the plurality of gate contacts, and a second conducting layer having a first portion, a second portion, and a third portion directly contacts a top surface of each of the plurality of TS contacts, the first and second conducting layers being physically separate by the dielectric and distinct from each other, wherein the first, second, and third portions of the second conducting layer are separated from each other by the plurality of gate contacts.
A semiconductor structure for performing static random access memory (SRAM) density scaling, the structure comprising:
- a plurality of gate contacts and a plurality of trench silicide (TS) contacts formed disposed in an alternating manner over a semiconductor substrate;
- gap regions formed after recessing the plurality of TS contacts;
- a dielectric for selectively filling only the gap regions of the plurality of recessed TS contacts;
- a common first metal layer disposed over and directly contacting the plurality of gate contacts;
- and
- a second metal layer having a first portion, a second portion, and a third portion disposed after the dielectric is recessed and after the first metal layer is formed, the second metal layer contacting a top surface of each of the plurality of TS contacts, and the first and second metal layers being physically separate by the dielectric and distinct from each other, wherein the first, second, and third portions of the second metal layer are separated from each other by the plurality of gate contacts.
Dependencies are inferred from the claim text.