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US 10,593,675 B2Granted
Method of maintaining the state of semiconductor memory having electrically floating body transistor
AssigneeZeno Semiconductor, Inc.
InventorsYuniarto Widjaja, Zvi Or-Bach
Life of this patent
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Abstract
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
Claims20
An integrated circuit comprising:
- an array of semiconductor memory cells, the array comprising:
- a plurality of said semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
- a first bipolar device having a first floating base region, a first collector, and a first emitter, and
- a second bipolar device having a second floating base region, a second collector, and a second emitter,
- wherein said first floating base region is common to said second floating base region;
- wherein said first collector is common to said second collector;
- wherein a state of each of said at least two of said memory cells is maintained through a back-bias applied to said first and second collectors, and
- wherein said first and second collectors are commonly connected to said at least two of said memory cells;
- a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors;
- and
- a control circuit configured to apply said back-bias to said first and second collectors.
8 more elements
An integrated circuit comprising:
- an array of semiconductor memory cells, the array comprising:
- a plurality of said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
- a first bipolar device having a first floating base region, a first collector, and a first emitter, and
- a second bipolar device having a second floating base region, a second collector, and a second emitter;
- wherein said first floating base region is common to said second floating base region;
- wherein said first collector is common to said second collector;
- wherein application of back-bias to said first and second collectors results in at least two stable floating base region charge levels, and
- wherein said first and second collectors are commonly connected to at least two of said memory cells;
- a region extending from and electrically connected to said first and second collectors, wherein said region has a conductivity type selected from a p-type conductivity type and an n-type conductivity type that is the same as a conductivity type of said first and second collectors;
- and
- a control circuit configured to apply said back-bias to said first and second collectors.
8 more elements
An integrated circuit comprising:
- an array of semiconductor memory cells, the array comprising:
- a plurality of said semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said plurality of semiconductor memory cells includes:
- a first bipolar device having a first floating base region, a first collector, and a first emitter;
- and
- a second bipolar device having a second floating base region, a second collector, and a second emitter;
- wherein said first floating base region is common to said second floating base region;
- wherein said first collector is common to said second collector;
- and
- wherein states of said semiconductor memory cells are maintained upon repeated read operations;
- a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors;
- and
- a control circuit configured to apply back-bias to said first and second collectors.
9 more elements
Dependencies are inferred from the claim text.