Deep fence isolation for logic cells
AssigneeGlobalfoundries Inc.
InventorsMing-Cheng Chang, Nigel Chan, Elliot John Smith
Life of this patent
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Abstract
Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.
Claims20
A structure comprising:
- a first logic cell including a first field-effect transistor and a second field-effect transistor;
- a first well defining a first back gate that is arranged beneath the first field-effect transistor and the second field-effect transistor;
- a dielectric layer arranged between the first well and the first logic cell;
- and
- a plurality of deep trench isolation regions extending through the dielectric layer and arranged to surround the first field-effect transistor, the second field-effect transistor, and the first well,
- wherein the first back gate is shared by the first field-effect transistor and the second field-effect transistor.
A method comprising:
- forming a first well in a substrate of a silicon-on-insulator wafer;
- forming a plurality of deep trench isolation regions extending through a buried insulator layer of the silicon-on-insulator wafer and arranged to surround the first well;
- and
- forming a first field-effect transistor and a second field-effect transistor of a first logic cell using a device layer of the silicon-on-insulator wafer and arranged over the first well,
- wherein the buried insulator layer of the silicon-on-insulator wafer is arranged between the first well and the first logic cell, and the first well defines a first back gate that is shared by the first field-effect transistor and the second field-effect transistor.
Dependencies are inferred from the claim text.