Nanosheet with single epitaxial stack forming off-set dual material channels for gate-all-around CMOS

A semiconductor structure comprising:

• an nFET device region comprising an nFET nanosheet stack of suspended silicon channel material nanosheets located entirely above a p-type silicon punch through stop layer that is present directly on a first portion of a silicon substrate having a first height;
• and
• a pFET device region located laterally adjacent the nFET device region and comprising a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets located entirely above an n-type doped silicon germanium alloy layer that is present directly on a second portion of the semiconductor substrate having a second height that is greater than the first height, wherein each suspended silicon channel material nanosheet in the nFET device region is vertically and horizontally off-set by one nanosheet from each silicon germanium alloy channel material nanosheet in the pFET device region, and the p-type silicon punch through stop layer is vertically and horizontally off-set from the n-type doped silicon germanium alloy layer, and wherein the n-type doped silicon germanium alloy layer has a topmost surface that is coplanar with a bottommost surface of a bottommost silicon channel material nanosheet of the suspended silicon channel material nanosheets and a bottommost surface that directly contacts the second portion of the semiconductor substrate and is coplanar with a topmost surface of the p-type silicon punch through stop layer.