Methods of manufacturing integrated circuit devices having a fin-type active region

A method of manufacturing an integrated circuit device comprising:

• forming a first fin-type active region and a second fin-type active region on a substrate;
• forming a first gate insulating layer and a second gate insulating layer on the first fin-type active region and the second fin-type active region, respectively, the first and second gate insulating layers including the same material and having substantially the same thickness;
• forming a third gate insulating layer on the second gate insulating layer;
• and
• depositing a first gate electrode and a third gate electrode on the first gate insulating layer and the third gate insulating layer, respectively, the third gate insulating layer being between the second gate insulating layer and the third gate electrode,
• wherein the first gate electrode has a first thickness in a first direction perpendicular to an upper surface of the substrate, and the third gate electrode has a second thickness that is different from the first thickness in the first direction.

A method of manufacturing an integrated circuit device comprising:

• forming a first fin-type active region and a second fin-type active region on a substrate;
• forming a first gate insulating layer and a second gate insulating layer on the first fin-type active region and the second fin-type active region, respectively, the first and second gate insulating layers including the same material and having substantially the same thickness;
• forming a third gate insulating layer on the second gate insulating layer;
• depositing a first gate electrode and a third gate electrode on the first gate insulating layer and the third gate insulating layer, respectively, the third gate insulating layer being between the second gate insulating layer and the third gate electrode;
• and
• annealing the first gate electrode and the third gate electrode,
• wherein the first gate electrode has a first thickness in a first direction perpendicular to an upper surface of the substrate, and the third gate electrode has a second thickness that is different from the first thickness in the first direction.