Method of forming a heterojunction semiconductor device having integrated clamping device

A cascode switch structure, comprising:

• a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode;
• a semiconductor MOSFET device having a third current carrying electrode electrically coupled to the first current carrying electrode, a fourth current carrying electrode electrically coupled to the first control electrode, and a second control electrode;
• a first diode having a first cathode electrode electrically coupled to the second current carrying electrode and a first anode electrode;
• and
• a second diode having a second anode electrode electrically coupled to the first anode electrode and a second cathode electrode electrically coupled to the fourth current carrying electrode, wherein the first diode has a greater breakdown voltage than that of the second diode.

A semiconductor device structure comprising:

• a semiconductor substrate having a first major surface and an opposing second major surface;
• a heterostructure adjacent the first major surface, the heterostructure comprising:
• a channel layer;
• and
• a barrier layer over the channel layer;
• a first electrode disposed proximate to a first portion of the channel layer;
• a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode;
• a third electrode disposed on the second major surface of the semiconductor substrate;
• a first control electrode disposed between the first electrode and the second electrode and configured to control a first current path between the first electrode and the second electrode;
• a fourth electrode disposed at least in part proximate to the first major surface, wherein the fourth electrode is electrically coupled to the first electrode;
• and
• a clamping device disposed in the semiconductor substrate and electrically coupled to the fourth electrode, wherein the clamping device comprises a plurality of n-type regions and a plurality of p-type regions disposed in the semiconductor substrate in a back-to-back p-n diode configuration.