Field effect transistor (FET) structure with integrated gate connected diodes

A structure, comprising:

• a plurality of field effect transistor cells, each one of the cells comprising:
• a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a semiconductor region of the structure between the source region and the drain region;
• wherein the gate electrodes of the cells are parallel one to another;
• and wherein the gate electrodes have ends thereof connected to a common gate manifold contact pad;
• a diode having:
• an electrode in ohmic contact with a different portion of the semiconductor region to provide a cathode for the diode, the diode region being disposed between the drain region of one of the cells and the drain region of an adjacent one of the cells, said cathode electrode being electrically connected to the drain region of said one of the cells and the drain region of an said adjacent one of the cells through portions of the semiconductor region between said drain region of one of the cells and said drain region of an adjacent one of the cells;
• and
• a Schottky electrode providing an anode for the diode;
• and
• wherein one of the cathode and anode being connected to the common gate manifold contact pad;
• and
• wherein the source region, the drain region, the channel region, and the diode region are disposed along a common line.