Semiconductor device having a plurality of chips being stacked

A semiconductor device, comprising:

• a first semiconductor chip including
• a first substrate,
• a first via penetrating through the first substrate,
• a first rear surface-side pad formed on a rear surface side of the first substrate and connected to the first via,
• a first wiring layer formed on the front surface side of the first substrate,
• a first front surface-side pad formed on the front surface side of the first wiring layer,
• a first CMOS circuit formed in the first substrate,
• a second CMOS circuit formed in the first substrate,
• a fourth front surface-side pad formed on the front surface side of the first wiring layer and has a size greater than the first front surface-side pad and connected to a certain power wire,
• an input signal wire provided in the first wiring layer which connects the first via, the first front surface-side pad, and an input terminal of the first CMOS circuit, and which does not connect to an output terminal of the second CMOS circuit, and
• a selector circuit configured to select one of a signal from the fourth surface-side pad and a signal from the first CMOS circuit;
• and
• a second semiconductor chip including
• a second substrate,
• a second via penetrating through the second substrate,
• a second rear surface-side pad formed on a rear surface side of the second substrate and connected to the second via,
• a second wiring layer formed on a front surface side of the second substrate,
• a third CMOS circuit formed in the second substrate, and
• an output signal wire formed in the second wiring layer which connects the second via to an output terminal of the third CMOS circuit,
• the first semiconductor chip is stacked on a rear surface side of the second semiconductor chip, and the second rear surface-side pad of the second semiconductor chip and the first front surface-side pad of the first semiconductor chip are connected to each other,
• the input terminal of the first CMOS circuit is connected to a gate terminal of the first CMOS circuit, and
• the output terminals of the second and third CMOS circuits are connected to drain terminals of the second and third CMOS circuits respectively.