Package method and package structure of fan-out chip

A package structure of a fan-out chip, comprising:

• a first chip, wherein the first chip is connected electrically with one or more bumps;
• a second chip, wherein the second chip is not connected electrically with bumps, wherein a first dielectric layer is formed on a surface of the second chip, and wherein a plurality of through-holes [fabricated in the first dielectric layer;
• a plastic package material filled in a space between the first chip and the second chip and the bumps over the first chip, wherein a height of the plastic package material does not exceed either heights of said bumps or a height of the first dielectric layer, such that the one or more bumps of the first chip and the plurality of through-holes in the first dielectric layer on the surface of the second chip are exposed from top during filling of the plastic package material;
• a second dielectric layer disposed over the first chip and the second chip, wherein the second dielectric layer is patterned to have first openings each aligned to one of the bumps connecting to the first chip, and to have second openings each aligned one of the plurality of through-holes over the second chip;
• a metal redistribution layer disposed on the second dielectric layer, wherein the metal redistribution layer fills in the first openings and the second openings, wherein the metal redistribution layer is patterned to connect electrically the one or more bumps of the first chip with the second chip;
• under-bump metallization layers on the metal redistribution layer;
• and a plurality of micro-bumps formed on the metal redistribution layer;
• wherein the plurality of micro-bumps connects electrically with the first chip through the metal redistribution layer filled in the first openings and the one or more bumps of the first chip, and wherein the plurality of micro-bumps connects electrically with the second chip through the metal redistribution layer filled in the first openings.