Multi-device packages and related microelectronic devices
AssigneeMicron Technology, Inc.
InventorsShih-Fan Kuan, Yi-Jen Lo
Life of this patent
Estimating the term…
Abstract
A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.
Claims22
A multi-device package, comprising:
- at least two device regions located within and comprising material of a wafer, the at least two device regions being laterally separated from one another within a common wafer;
- conductive pads recessed within the wafer;
- a first redistribution layer located directly on an upper surface of the wafer and electrically connected to the at least two device regions through the conductive pads, the at least two device regions being electrically integrated with one another through the first redistribution layer, wherein the conductive pads comprise an uppermost metal material of a metal interconnect structure of the first redistribution layer;
- an external chip located on the first redistribution layer;
- and
- first connectors located between the first redistribution layer and the external chip to interconnect the first redistribution layer and the external chip.
A multi-device package, comprising:
- at least two device regions located within and comprising material of a wafer, the at least two device regions being laterally separated from one another within a common wafer;
- a first redistribution layer located directly on an upper surface of the wafer, the first redistribution layer electrically integrating the at least two device regions;
- an external chip located on the first redistribution layer;
- a second redistribution layer located over the first redistribution layer;
- and
- a molding material located between the first redistribution layer and the second redistribution layer, the molding material comprising:
- a first conductive contact through the molding material;
- and
- a second conductive contact through the molding material and through openings within the external chip, and the first conductive contact and the second conductive contact interconnecting the first redistribution layer and the second redistribution layer.
A microelectronic device, comprising:
- a wafer comprising conductive pads recessed within the wafer;
- at least two device regions located within the wafer, the at least two device regions comprising material of the wafer and being laterally separated from one another within the same wafer;
- a first redistribution layer located directly on an upper surface of the wafer, the first redistribution layer electrically connected to the at least two device regions to electrically integrate the at least two device regions, wherein the conductive pads comprise an uppermost metal material of a metal interconnect structure of the first redistribution layer;
- first connectors located on the first redistribution layer;
- an external chip located on the first connectors, the external chip electrically connected to the first redistribution layer with the first connectors.
Dependencies are inferred from the claim text.