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US 10,593,631 B2Granted
Warping reduction in silicon wafers
AssigneeOracle International Corporation
InventorJeewika Ranaweera
Life of this patent
Estimating the term…
Abstract
Techniques for reducing stress in an integrated circuit wafer are disclosed. A silicon substrate may include multiple integrated circuit chips and multiple scribe regions situated between the one of the multiple integrated circuit chips. A particular scribe region includes a plurality of layers and a stress reduction structure that includes, at a particular layer of the plurality of layers, a material whose coefficient of thermal expansion of materials is greater than a coefficient of thermal expansion of the silicon wafer.
Claims11
An integrated circuit wafer, comprising:
- a silicon substrate that includes:
- a plurality of integrated circuit chips;
- and
- a plurality of scribe regions situated between ones of the plurality of integrated circuit chips, wherein a particular scribe region of the plurality of scribe regions has a total area and includes a plurality of vertically stacked layers, wherein the particular scribe region includes a stress reduction structure located on at least a particular layer of the plurality of vertically stacked layers, wherein the stress reduction structure includes, on the particular layer, a material, wherein a collective area of the material on the particular layer is at least 40 percent of the total area of the particular scribe region, and wherein the material is metal that is electrically isolated from one or more metal regions included in the plurality of integrated circuit chips adjacent to the particular scribe region, and has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the silicon substrate.
1 more element
An apparatus, comprising:
- a silicon substrate that includes:
- a plurality of integrated circuit chips;
- and
- a plurality of scribe regions situated between one of the plurality of integrated circuit chips, wherein a particular scribe region of the plurality of scribe regions includes:
- a plurality of vertically stacked layers;
- a stress reduction structure located on at least a particular layer of the plurality of vertically stacked layers, wherein the stress reduction structure includes, on the particular layer, a material, wherein a collective area of the material on the particular layer is at least 40 percent of a total area of the particular scribe region, and wherein the material is metal that is electrically isolated from one or more metal regions included in the plurality of integrated circuit chips adjacent to the particular scribe region, and has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the silicon substrate;
- a test circuit;
- and
- one or more mask alignment targets.
6 more elements
Dependencies are inferred from the claim text.