Fan-out package with multi-layer redistribution layer structure
AssigneeAdvanced Micro Devices, Inc.
InventorsRahul Agarwal, Milind S. Bhagavat, Priyal Shah
Life of this patent
Estimating the term…
Abstract
Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.
Claims14
A semiconductor chip device, comprising:
- a redistribution layer (RDL) structure including plural metallization layers and plural polymer layers, one of the polymer layers being positioned over one of the metallization layers, the one of the metallization layers having conductor traces, the one of the polymer layers having an upper surface that is substantially planar at least where the conductor traces are positioned;
- a semiconductor chip positioned on and electrically connected to the RDL structure;
- a molding layer positioned on the RDL structure and at least partially encasing the semiconductor chip;
- and
- a warpage compensation structure positioned on the molding layer, the warpage compensation structure including a cap substrate and a polymer layer positioned on the cap substrate.
A semiconductor chip device wafer, comprising:
- plural redistribution layer (RDL) structures including plural metallization layers and plural polymer layers, one of the polymer layers being positioned over one of the metallization layers, the one of the metallization layers having conductor traces, the one of the polymer layers having an upper surface that is substantially planar at least where the conductor traces are positioned;
- plural semiconductor chips, each of the semiconductor chip being positioned on and electrically connected to one of the RDL structures;
- a molding layer positioned on the RDL structures and at least partially encasing the semiconductor chips;
- and
- a warpage compensation structure positioned on the molding layer, the warpage compensation structure including a cap substrate and a polymer layer positioned on the cap substrate.
A method of manufacturing a semiconductor chip device, comprising:
- fabricating a redistribution layer (RDL) structure including plural metallization layers and plural polymer layers, one of the polymer layers being positioned over one of the metallization layers, the one of the metallization layers having conductor traces;
- planarizing one of the polymer layers to have an upper surface that is substantially planar at least where the conductor traces are positioned;
- positioning a semiconductor chip on the RDL structure and electrically connecting the semiconductor chip to the RDL structure;
- forming a molding layer on the RDL structure and at least partially encasing the semiconductor chip;
- and
- coupling a warpage compensation structure on the molding layer, the warpage compensation structure including a cap substrate and a polymer layer on the cap substrate.
Dependencies are inferred from the claim text.